EVBUM2277/D
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2
Figure 1. Serial Input Timing
SLOAD_INPUT
SDATA_INPUT
SCLK_INPUT
DS2
DS1
DS0
R/W
A0
A1
A2
A3 (or T
est)
D0
D1
D2
D3
D4
Dn
…
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
(decoded PLD output)
SLOAD_xxx
The first 3 bits in the datastream are the Device Select bits
DS[2..0], sent MSB first, as shown in Figure 1. The Device
Select bits are decoded as shown in Table 2.
The next bit in the datastream is the Read/Write bit (R/W).
Only writing is supported; therefore this bit is always LOW.
The definition of next four bits in the datastream depends
on the device being addressed with the Device Select bits.
For the KSC−1000 device, they are Register address bits
A[0..3], LSB first. For the AD9845A AFE, they are Register
Address bits A[0..2], LSB first, followed by a Test bit which
is always set LOW.
The remaining bits in the bitstream are Data bits, LSB
first, with as many bits as are required to fill the appropriate
register.
AFE Default Initialization
Upon power up, or when the BOARD_RESET button is
pressed, the PLD programs the registers of the two AFE
chips on the Timing Generator Board to their default settings
via the 3-wire serial interface. See Table 9 for details.
The AD9845A AFE must be reprogrammed on power-up,
as it does not retain register settings when power is removed.
Figure 2. AFE Initialization Timing
R/W
A0
A1
A2
T
est
D0
D1
D3
D4
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
SLOAD_AFE_x
SDATA
SCLK
D5
D6
D7
D8
D9
D10
D2
The data for each AFE register is formatted into two bytes
of data, as shown in Figure . The Read/Write bit is always
low, and the Address bits specify the register being
programmed, as shown in Table 9. Each byte is read into an
8-bit shift register, and is shifted out as a serial stream of
eight bits. Each register in the AFE is programmed in this
fashion until the entire AFE is programmed.
KSC−1000 Default Initialization
Upon power-up, or when the BOARD_RESET button is
pressed, the Altera PLD programs the registers of the
KSC−1000 chip on the AFE Timing Generator Board to
their default settings via the 3-wire serial interface.
The default settings are selected by the user through the PLD
inputs SW[7..0] and DIO[15..0] (See Table 10 through
Table 24 for details). The KSC−1000 must be
reprogrammed on power-up, as it does not retain register
settings when power is removed.
The KSC−1000 default settings automatically
programmed by the PLD allow the Evaluation Board Kit
user to operate the CCD image sensor with minimal
intervention and no programming. The default settings are
chosen to comply with the CCD device specification (See
References
). The registers, line tables and frame tables
described in this document also serve as examples for those
who wish to create their own KSC−1000 timing.
