EVBUM2277/D
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8
Table 11. REGISTER 1 DEFAULT SETTING
(continued)
Register Entry
Data (2-channel)
Data (1-channel)
DATACLK1_Enable
1
1
DATACLK2_Enable
1
1
PIXCLK_Enable
1
1
H3_Enable
1
1
H1_Enable
1
1
H2_Enable
1
1
SH1_Enable
1
1
SH3_Enable
1
1
H6 24 mA Output Enable
0
0
H4 24 mA Output Enable
0
0
H5 24 mA Output Enable
0
0
RG 24 mA Output Enable
0
0
SH2 24 mA Output Enable
0
0
SH4 24 mA Output Enable
0
0
DATACLK1 24 mA Output Enable
0
0
DATACLK2 24 mA Output Enable
0
0
H3 24 mA Output Enable
0
0
H1 24 mA Output Enable
0
0
H2 24 mA Output Enable
0
0
SH1 24 mA Output Enable
0
0
SH3 24 mA Output Enable
0
0
DLL Frequency Range Select
8
8
Register 2: General Control
Register 2 controls the Power Management and
Operation state of the KSC−1000. The Low Power Mode is
not used on the KAI−2093, so this bit is always LOW.
The Memory Table Mode bit is used to halt execution of the
KSC−1000 timing sequences and to enable programming of
the registers. The KSC−1000 Initialization sequence begins
with setting the Memory Table Mode bit in Register 2 to
Program Mode, and ends by setting the bit to Execution
Mode. See the KSC−1000 Device Specification
(
References
) for more details.
Table 12. REGISTER 2 SETTINGS
Register Entry
Program Mode
Execution Mode
Low Power Enable
0
0
Memory Table Mode
0
1
Register 3: INTG_START Setup
The default settings written to Register 3 establish the
setup, pulsewidth, and hold timing of the Electronic Shutter
pulse. The Shutter Pulse may occur on a particular line, as
controlled by Register 4, or may be asserted by setting the
“Force INTG_STRT” bit in the Frame Table (Register 8). In
either case, the Electronic Shutter Pulse occurs before the
vertical clocking interval of the Frame Table entry
(Figure 12).
Table 13. REGISTER 3 DEFAULT SETTING
Register Entry
Data
Electronic Shutter Setup Clocks[0..9]
30
Electronic Shutter Pulse Width[0..9]
200
Electronic Shutter Hold Clocks[0..9]
30
