EVBUM2277/D
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17
Figure 10. Frame Table 0 Default Timing
V1_CCD
V2_CCD
H1A_CCD
H2A_CCD
PBLK
VD_TG
FRAME_VALID
LINE_VALID
FT0 Entry
2
0
1
0
Line Table
1
1104
Counts
1
4
x
CLPOB1
(not to scale)
INTEGRATE
DIODE_TRANSFER
V_TRANSFER
PLD STATE
TIMED_INTEGRATION
Frame Table 1 Sequence
Frame Table 1 contains the 2
×
2 Binning Mode timing
sequence used to sum the charge collected in four photosites
into one CCD pixel. The sequence is identical to that of
Frame Table 0, except that the Vertical Clocks are asserted
twice per line, which dumps charge from two vertical CCD
pixels into each Horizontal register CCD pixel.
Figure 11. Frame Table 1 Default Timing
V1_CCD
V2_CCD
H1A_CCD
H2A_CCD
PBLK
VD_TG
FRAME_VALID
LINE_VALID
FT1 Entry
2
0
1
0
Line Table
1
610
Counts
1
5
x
CLPOB1
(not to scale)
INTEGRATE
DIODE_TRANSFER
V_TRANSFER
PLD STATE
TIMED_INTEGRATION
Electronic Shutter Timing
The electronic shutter timing is controlled by the values in
Register 3 of the KSC−1000. There are two methods of
actuating the Electronic Shutter pulse: by setting the
Integrate Start Pulse Line Number value in Register 4 so
that the pulse occurs on a specific line, or by setting the
Force INTG_START bit in a Frame Table entry. In either
case, the Electronic Shutter pulse setup, width, and hold
times are determined by the values in Register 3. The shutter
sequence is inserted before the specified line, causing that
particular line time to be extended accordingly.
If the Integrate Start Pulse Line Number value in
Register 4 is set to 0, the Electronic Shutter will occur
immediately following the Diode Transfer sequence, before
the first line is read out. If the Integrate Start Pulse Line
Number value is greater than the number of vertical lines in
the Frame Table, there will be no Electronic Shutter. This is
the method used to disable the Electronic Shutter.
