EVBUM2277/D
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14
KAI−2093 TIMING
Line Table 0 (Line Transfer)
Line Table 0 is the Line Transfer timing sequence that
transfers one entire row of charge toward the horizontal
register. V1 and V2 are asserted, with overlap adjustability
to compensate for the clock driver rise and fall times. Charge
is moved down the vertical CCD registers, and the last row
of charge is dumped into the horizontal register. The VCCD
clocking interval is followed by the Horizontal clocks,
which shift one line out through the output amplifier(s).
Figure 4. Line Table 0 Default Timing
LT0 Entry
V1_CCD
V2_CCD
0
1
2
3
5
1
3
30
2
1
30
Pix Counts
(not to scale)
HCLK_ENABLE
VLOW
VMID
VLOW
VMID
H1A_CCD
H2A_CCD
4
T
VD
T
VCCD
T
HD
Symbol
Line Table 1 (Diode Transfer)
Line Table 1 is the Photodiode Transfer timing, in which
the V2 clock 3
rd
-level shifts charge from all the photodiodes
into the vertical CCD registers. The V1 and V2 clocks have
overlap adjustability to compensate for the clock driver rise
and fall times.
Figure 5. Line Table 1 Default Timing
LT1 Entry
V1_CCD
V2_CCD
0
1
2
3
4
5
6
1
500
6
240
1
400
1310
Pix Counts
(not to scale)
HCLK_ENABLE
VLOW
VLOW
VMID
VMID
VHIGH
H1A_CCD
H2A_CCD
T
3P
T
V3rd
T
3D
T
3FD
Symbol
