EVBUM2277/D
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16
Frame Table 0 Sequence
Frame Table 0 contains the Free-Running (video mode)
timing sequence used to continuously read out all rows of the
CCD. The sequence begins with the Line Transfer sequence,
followed by the Timed Integration sequence. When
integration is complete, the Altera PLD asserts the VD_TG
signal to the KSC−1000. This initiates the Photodiode
transfer, and the cycle repeats with the next Line Transfer
sequence.
Execute LT1
(DIODE XFR)
Count = 1
DIO[11..7] =
{1,2,...7}?
Set INTEGRATE
Wait for INT ctr
Execute LT0
(LINE XFR)
Count = 1214
Wait for
FRAME_VALID
(falling edge)
Execute LT5
Wait for VD_TG
Issue VD_TG
Reset INTEGRATE
VD_TG
INTG_START
Shutter?
Issue
INTG_START
Set INTEGRATE
on INTG_START
(falling edge)
Wait for FRAME_VALID
(rising edge)
Altera PLD
KSC−1000TG
No
Yes
State Machine Sequence
Frame Table 0 Sequence
FRAME_VALID
V_TRANSFER
TIMED_
INTEGRATION
DIODE_
TRANSFER
ENTRY 0
ENTRY 1
ENTRY 2
ENTRY 3
Jump to FT0 Entry 0
Count = 1
FRAME_VALID
Figure 9. Free-Running Mode Timing Sequence
