No.13S080-10
19
STC-CMB200PCL / STC-CMC200PCL / STC-CMB401PCL / STC-CMC401PCL
Specifications and Users guide
5. The camera output timing charts
5.1. The horizontal timings (STC-CMB/CMC200PCL, CMB/CMC401PCL)
As for the vertical timing, please refer to
5.2.
エラー
!
ブックマークが自己参照を行っています。
.
Highs Speed
Clock and Low Speed Clock are existed as Pixel Clock.
51.1 2 Taps (1X2-1Y) / Horizontal 2,048 pixels
1 CLK = 11.764 nseconds(85MHz)
1 CLK = 23.524 nseconds(42.5MHz)
The pixel order for the Image
TAP1: DA output pixels
TAP2: DB output pixels
LED
Video out
(Tap 1: DA)
LVAL
Horizontal
blanking
1,032 CLK
One horizontal (1H)
1,024 CLK
8 CLK
Video output
8 CLK
Video out
(Tap 2: DB)
1
3
5
2
4
6
20
43
20
45
20
47
20
44
20
46
20
48
1
3
5
7
......
2035
9
11
13
2037 2039 2041 2043 2045 2047
2
4
6
8
......
2036
10
12
14
2038 2040 2042 2044 2046 2048
1
2
2,048 pixels
3
4
......
2042
5
6
7
8
9
10
11
12
13
14
2043 2044 2045 2046 2047 2048
2
,048 line
s
(STC
-
C
M
B
4
MC
L/
C
MC4M
CL)
1
,088 line
s
(STC
-
C
M
B
2
MC
L/
C
MC2M
CL)
For more information please contact Aegis Electronic Group, Inc. *(888)687-6877 *[email protected] *http://www.aegiselect.com
Aegis
Electronic
Group,
Inc.
