NXP Semiconductors MC92602, User Manual, Page: 7 / 48

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor 1-1
Chapter 1
General Information
1.1 Introduction
This user’s guide describes the MC92602 design verification board, Rev. B and higher. The design
verification board (DVB) facilitates the full evaluation of the MC92602 Quad Reduced Interface SerDes.
It should be read in conjunction with the
MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference
Guide . This design verification board is intended for evaluation and testing purposes only. Freescale does
not guarantee its performance in a production environment.
This board was designed to be used with laboratory equipment (pattern generators, data analyzers, BERT,
scopes, etc.) or connected to other evaluation boards. Access to the MC92602 device (verification chip) is
through connectors to each pin, to allow complete in-depth ‘design verification’ testing of the chip design.
This allows the user to check any or all features/functions of the MC92602 device.
The four parallel data input ports and all configuration/control signal pins, are accessed through common
2
×
10, 0.100" male connectors (headers). The parallel data output ports are accessed through 2
×
20, 0.100"
connectors. Device JTAG port signals are also accessed with a separate connector.
The MC92602 high-speed serial receivers and transmitters are accessed via SMA coaxial connectors for
signal integrity measurements.
A single 5.0-V power source is required for the DVB operation. All necessary voltages are generated by
regulators onboard. The reference clock for the MC92602 chip may be provided using either an external
clock or the onboard crystal oscillator. Clock drivers on the DVB provide additional clock signals for
triggering analyzer instrumentation and scopes.
1.2 Design Verification Board Features
The functional, physical, and performance features of the MC92602DVB are as follows:
• A single external 5.0-V to onboard regulators supply power to all onboard circuitry.
• Reference clock source is a 250-MHz crystal oscillator or an external clock source.
• Parallel data and control interfaces accessible through standard 0.100", 2 row connectors for data
generators and analyzers.
• The full-duplex differential data links accessible through SMA connectors.
• Two pairs of 50-
Ω
test traces with SMA connections facilitate TDR measurements of the
characteristic impedance of representative board traces.
• Connector provided for JTAG test access port