NXP Semiconductors MC92602, User Manual, Page: 24 / 48

Laboratory Equipment and Quick Setup Evaluation
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
3-6 Freescale Semiconductor
3.2.3 Quick Setup Bit Error Rate Checking
In addition to having an integrated PN generator, the MC92602 also has a bit error rate checker (BERC).
An integrated 23rd order signature analyzer, that is synchronized to the incoming PN stream is used to
count code group mismatch errors relative to the internal PN reference pattern. The following test
procedure will describe how to use this BIST feature. For more information concerning the MC92602
BIST, refer to the
MC92602 Quad 1.25 Gbaud Reduced Interface SerDes Reference Guide .
3.2.3.1 Equipment Setup
Connect the MC92602DVB as shown in Figure 3-3 , connecting the transmitter outputs of the link under
test (XLINK_ x _P/N) to the receiver under test (RLINK_ x _P/N).
NOTE
The receiver signature analyzers assume all four channels are being
exercised. If BIST testing is being performed between devices, or by means
of external loopback on selected channels, the unused channel receivers
must be disabled or the analyzers will not go into the PN Sync state. That is,
receivers not having a PN stimulus must have XCVR_
x _DISABLE
asserted.
Figure 3-3. Bit Error Rate Check Test Setup
XLINK_A_N
XLINK_A_P
MC92602DVB
+5-V Supply
+5-V GND +5-V
GND
+5 V GND
RLINK_D_N
RLINK_D_P
XLINK_D_N
XLINK_D_P
D_RECV
C_RECV
B_RECV
A_RECV
CH 1
CH 2
CH 3
CH 4
Sense Force Sense
Force
Logic
Analyzer
RLINK_C_N
RLINK_C_P
XLINK_C_N
XLINK_C_P
RLINK_B_N
RLINK_B_P
XLINK_B_N
XLINK_B_P
RLINK_A_N
RLINK_A_P