NXP Semiconductors MC92602, User Manual, Page: 26 / 48

Laboratory Equipment and Quick Setup Evaluation
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
3-8 Freescale Semiconductor
7. Once the receiver has initially locked all receiver data bits, RECV_ x _[4:0], are set to zero (logic
low). Should an error occur, RECV_ x _[4:0] will increment by one and RECV_ x _ERR will flag the
error during that byte time. The value of RECV_ x _[4:0] remains constant until another error is
detected or the system is reset. If the receiver counter fills with errors, all bits of RECV_ x _[4:0]
stay a logic high (11111111) until the receiver is reset. Refer to the MC92602 Quad 1.25 Gbaud
Reduced Interface SerDes Reference Guide for more detail.
Figure 3-4. Receiver Startup and Error Detection Sequence
BIST
Counted
3 PN Mismatches
Running
RECV_x_RCLK
RECV_x_ERR
RECV_x_K
RECV_x_3
RESET
RECV_x_1
RECV_x_0
RECV_x_2
MC92602
in Reset
RCVR BIST Not Byte
Not Locked
PN Analyzer
Synced
This Character
No PN Mismatch
Running
Startup
RCVR in
Sync