NXP Semiconductors MC92602, User Manual, Page: 31 / 48

Test Setups
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor 4-5
4.2.3 Reference Clock Jitter Tolerance Test
The test setup, as shown in Figure 4-5 , is used to observe the amount of jitter placed on the reference clock
that does not produce errors on the serial data outputs as compared to the input serial data stream. The
MC92602 is placed in ten-bit interface mode (TBIE) and repeater mode (REPE). The serial data stream
can be set to either PRBS or user-defined data. The control bits are set as follows:
• REPE = ‘1’
• TBIE = ‘1’
All other control inputs are set to ‘0.’
Figure 4-5. Reference Clock Jitter Tolerance Test Setup
RF Source
70000 Mainframe
with Microwave
Transition Analyzer
Ch1
Ch2
Function
Generator
Mo
du
la
ti
on
Si
g
n
a
l
10
-MHz Ref
e
rence Cl
oc
k
HPIB
CK Error Detector D
CK Pattern Generator D
Bit Error Rate Tester
Clean
Clock
1.25 GHz
Bit Error Rate Data over the HPIB
Power
Splitter
Jittered
Clock
1.25 GHz
Prescaler
Divide-by-10
MC92602DVB
Ser
ial Data
Jittered
Reference
Clock
125 MHz
Synthesized
Sweeper
(Carrier Frequency)
DC Blocker