BackCover
Page 1: ...MC92602 Reduced Interface SerDes Design Verification Board User s Guide MC92602DVBUG Rev 3 06 2005...
Page 2: ......
Page 3: ...2DVB Package Contents 2 1 2 3 Hardware Preparation 2 1 2 3 1 Setting the Power Supply and Voltage Regulators 2 1 2 3 2 Setting the Voltage Regulators 2 2 2 3 3 HSTL Voltage Reference Regulator 2 3 2 4...
Page 4: ...allel I O Connections 3 7 3 2 3 3 Quick Setup BERC Test Procedure 3 7 Chapter 4 Test Setups 4 1 Serial Link Verification Using a Serial Bit Error Rate Tester BERT 4 1 4 1 1 Test Setup for Full Speed M...
Page 5: ...erification Board User s Guide Rev 3 Freescale Semiconductor v Paragraph Page Number Title Number Appendix C Prescaler for Jitter Measurement C 1 Divide by xx Prescaler Description C 1 C 2 Prescaler C...
Page 6: ...MC92602 Reduced Interface SerDes Design Verification Board User s Guide Rev 3 vi Freescale Semiconductor...
Page 7: ...le connectors headers The parallel data output ports are accessed through 2 20 0 100 connectors Device JTAG port signals are also accessed with a separate connector The MC92602 high speed serial recei...
Page 8: ...nd link I O regulator 1 8 V 0 15 V DC Interface I O VDDQ regulator 2 5 V 0 2 or 3 3 V 0 3 V DC MC92602 package 196 MAPBGA Operating temperature 0 30 C Material FR 4 Dimensions Height 14 8 377 mm Width...
Page 9: ...ent Description MC92602ZT Freescale Quad 1 25 Gbaud Reduced Interface SerDes 2 10 0 100 connectors PG1 PG11 and PG13 provide access to the parallel inputs and control signals 2 20 0 100 connectors LA1...
Page 10: ...RECV_B RECV_C RECV_D XMIT_C XMIT_D Control 2 10 0 100 Connectors SW1 Connectors 1 5V_CLK_OUT5 1 5V_CLK_OUT6 CLK_IN RLINK_D0 RLINK_C0 RLINK_B0 RLINK_A0 XLINK_D0 XLINK_C0 XLINK_B0 XLINK_A0 TST1 TST2 TS...
Page 11: ...1 depicts the location of the major components on the board The following sections describe proper setup of the MC92602DVB 2 3 1 Setting the Power Supply and Voltage Regulators The MC92602DVB requires...
Page 12: ...rallel input and output interface circuitry This voltage level is determined by the desired logic interface The 1 5 V supply can be adjusted using a R22V1 potentiometer from 1 5 V 0 45 V 0 15 V If des...
Page 13: ...5 V VDDQ supply R22V2 should be set such that the voltage at the HSTL_VREF test point is 0 75 V For those systems whose HSTL voltage will be 1 8 V this potentiometer should be set to 0 9 V The R22V2...
Page 14: ...uit on the board via the CLK_IN SMA connector To supply an external reference clock switch number 2 on SW1 must be set to the off position The user must then supply a 1 0 Vp p input clock via the SMA...
Page 15: ...d 6 to either on divide by one or to off divide by 2 This allows the interface between the board and the bench to be either single data rate SDR with a double speed clock or double data rate DDR with...
Page 16: ...re are no bi directional signals on the MC92602 or on the design verification board 2 5 1 1 Parallel Inputs The parallel inputs both data and control are accessible via 2 10 0 100 connectors Figure 2...
Page 17: ...and 8 are connected to the ground 0 0 V plane 2 5 3 Serial Inputs and Outputs All MC92602 high speed serial differential inputs and differential outputs are connected to appropriately labeled pairs o...
Page 18: ...e Rev 3 2 8 Freescale Semiconductor 2 7 Test Traces The MCS92602DVB design verification board has both vertical and horizontal 50 test traces Vertical TST1 TST5 and TST2 TST6 Horizontal TST3 TST7 and...
Page 19: ...to the user For more information regarding the MC92602 feature set refer to the MC92602 Quad 1 25 Gbaud Reduced Interface SerDes Reference Guide 3 1 Recommended Laboratory Equipment Evaluation of the...
Page 20: ...ccessories SMA male each end coax patch cords lengths various SMA 3dB attenuators SMA 6db attenuators SMA DC blockers AC couplers 50 SMA terminations to ground SMA 50 feed through terminations 5 16 to...
Page 21: ...and observation of the data eye produced by the on chip PN generator requires only the MC92602DVB a power supply a high speed digital sampling scope 0 100 shunts and single pin receptacle patch cords...
Page 22: ...Level Connector Pin Signal Bias Level TEST_0 9 TDI GND A_XMIT0 1 XMIT_A_0 GND 11 TCK GND 3 XMIT_A_1 GND 13 TMS GND 5 XMIT_A_2 GND 15 TRST GND 7 XMIT_A_3 GND CTRL_SIG_0 1 REPE GND 9 XMIT_A_K 1 5 V 3 R...
Page 23: ...V regulators at connectors T10 T7 and T6 respectively If necessary adjust R12V R22V and R22V1 to obtain desired voltage levels 3 Verify that the reference clock frequency at CLK_OUT5 is 125 MHz period...
Page 24: ...2 3 1 Equipment Setup Connect the MC92602DVB as shown in Figure 3 3 connecting the transmitter outputs of the link under test XLINK_x_P N to the receiver under test RLINK_x_P N NOTE The receiver sign...
Page 25: ...ectors T10 T7 and T6 respectively If necessary adjust R12V R22V and R22V1 to obtain desired voltage levels 3 Verify that the reference clock frequency at CLK_OUT1 is 156 25 MHz period 6 4 ns 4 Connect...
Page 26: ...x_ 4 0 remains constant until another error is detected or the system is reset If the receiver counter fills with errors all bits of RECV_x_ 4 0 stay a logic high 11111111 until the receiver is reset...
Page 27: ...ate Tester BERT This test setup is used to observe the rate at which the MC92602 produces errors given either pseudo random PRBS patterns or user defined pattern sets generated by the serial bit error...
Page 28: ...g may also be performed using half speed mode HSE 1 This reduces all frequencies in the setup by a factor of two Figure 4 2 depicts the serial link test setup for using HSE and using a divide by 10 pr...
Page 29: ...jittered source The amplitude of modulation is then translated into jitter in units of peak to peak unit intervals UIp p Different synthesized sweepers have different characteristics at different freq...
Page 30: ...IE 1 All other control inputs are set to 0 The parallel data inputs must be set to the pattern shown in Figure 4 4 This data pattern appears as a 625 MHz clock signal at the serial outputs Figure 4 4...
Page 31: ...REPE The serial data stream can be set to either PRBS or user defined data The control bits are set as follows REPE 1 TBIE 1 All other control inputs are set to 0 Figure 4 5 Reference Clock Jitter To...
Page 32: ...tream can be set to either PRBS or user defined data The control bits are set as follows REPE 1 TBIE 1 All other control inputs are set to 0 Figure 4 6 Data Jitter Tolerance Test Setup RF Source 70000...
Page 33: ...pin must be jumper connected to 1 5 V VDDQ on the access connectors PG12 or PG14 If the input is required to be low a shorting jumper may be installed The signal name description and the MC92602 devi...
Page 34: ...12 TBIE Ten bit interface enable 9 C12 COMPAT IEEE 802 3 compatibility mode enable 11 N C 13 P9 RECV_REF_A Receiver A primary clock enable 15 N9 XMIT_REF_A Transmit A primary clock enable 17 N C 19 N...
Page 35: ...T0 Channel B C_XMIT0 Channel C D_XMIT0 Channel D 1 P5 N5 B5 A5 XMIT_x_0 Transmitter x data input bit 0 3 N6 P4 A4 B6 XMIT_x_1 Transmitter x data input bit 1 5 P6 N4 B4 A6 XMIT_x_2 Transmitter x data i...
Page 36: ...tion A_RECV Channel A B_RECV Channel B C_RECV Channel C D_RECV Channel D 1 N C N C N C N C 3 M2 K1 F1 C2 RECV_x_CLK XCVR_ x receive data clock 5 N C N C N C N C 7 M2 K1 F1 C2 RECV_x_CLK XCVR_ x receiv...
Page 37: ...nctions It is recommended that TRST be terminated in one of the following ways TRST be driven by a TAP controller that provides a reset after power up Connect TRST to RESET Terminate TRST with a 1 K r...
Page 38: ...Connector Signals MC92602 Reduced Interface SerDes Design Verification Board User s Guide Rev 3 A 6 Freescale Semiconductor...
Page 39: ...C21 100 F Kemet T495X107K010AS 100 F solid tantalum chip capacitor low ESR 10 V size 7343H 3 5 C5 C12 C13 C22 C23 10 F Kemet T495X106K035AS 10 F solid tantalum chip capacitor low ESR 35 V size 7343H...
Page 40: ...el shift and clock buffer 32 pin gull wing TQFP 20 9 T1 T9 N A SPC Technology 2304 2303 9648 9649 9650 4 mm screw terminal binding post red black yellow blue green 21 1 R67 68 Newark 50N1713 68 chip r...
Page 41: ...esistor J lead 33 3 R22V R22V1 R22V2 500 BOURNS 3214W 1 502E Surface mount trimming resistor J lead 34 1 U1 N A Freescale MC92602 Quad 1 25 Gbaud DDR SerDes in 196 MAPBGA 35 45 N A N A 3M 929950 00 0...
Page 42: ...Parts List MC92602 Reduced Interface SerDes Design Verification Board User s Guide Rev 3 B 4 Freescale Semiconductor...
Page 43: ...Block Diagram The input to the prescaler can be either through a divide by 2 or directly into the 5 bit programmable counter The bank 1 and bank 2 DIP switches can be used to select a variety of presc...
Page 44: ...or 8 MC100ELT23 On Semiconductor Newark Dual differential PECL to TTL translator with separate inputs MC100ELT21 On Semiconductor Newark Single differential PECL to TTL translator Alternative to above...
Page 45: ...e MC92602DVBUG Table D 1 provides a revision history for this document Table D 1 MC92602DVB Revision History Rev No Date Substantive Change s 1 5 30 2002 Initial release 1 1 10 1 2002 Editorial correc...
Page 46: ...Revision History MC92602 Reduced Interface SerDes Design Verification Board User s Guide Rev 3 D 2 Freescale Semiconductor...
Page 47: ...BackCover...
Page 48: ...particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including with...
