NXP Semiconductors MC92602, User Manual, Page: 25 / 48

Laboratory Equipment and Quick Setup Evaluation
MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
Freescale Semiconductor 3-7
3.2.3.2 Parallel I/O Connections
The bias connections for the parallel inputs to perform the quick setup BERC test are the same as those for
the quick setup eye-diagram and shown in
Table 3-4 .
The parallel outputs are connected to a data analysis system. The data analyzer may be used to observe the
start up sequence and the status and errors detected by the internal data analyzers.
3.2.3.3 Quick Setup BERC Test Procedure
1. Connect the MC92602DVB and test equipment as described in Section 3.2.3.1, “Equipment
Setup . ” This will place the MC92602 in PN generation mode with the MC92602 held in reset and
set the receivers to BERC mode using the recovered clock.
Steps 2 and 3 may be skipped if previously performed when setting up the DVB.
2. Apply +5.0 V to the evaluation board. Verify voltage levels of +3.3 V, +1.8 V, and +V
DDQ
(1.5 V)
regulators at connectors T10, T7, and T6, respectively. If necessary, adjust R12V, R22V, and
R22V1 to obtain desired voltage levels.
3. Verify that the reference clock frequency at CLK_OUT1 is 156.25 MHz
(period = 6.4 ns).
4. Connect the RESET (connector CTRL_SIG_0, pin 11) to a +1.5 V V
DDQ
access connection. This
releases the RESET signal.
5. Observe the parallel outputs on the data analyzer. As described in the MC92602 Quad 1.25 Gbaud
Reduced Interface SerDes Reference Guide, the MC92602 will start and lock the PLL, initialize
the receivers, perform byte alignment, and reset the bit error counter.
6. When the receivers are locked and BIST is running, the recovered clock is observable on
RECV_ x _RCLK. Refer to Table 3-5 for the receiver state sequence, which will occur on each
receiver’s status output. See Figure 3-4 for an example of a receiver start-up and error detection
sequence.
Table 3-5. State Sequence of Receiver
Receiver State
RECV_ x _ERR RECV_ x _K RECV_ x _RCLK
E
0
E
1
K
0
K
1
Edge
1 MC92602 is in reset mode Low Low Low Low Low
2 Receiver in startup High — Don’t care — ¦
— Low — Don’t care Ø
3. Receiver byte/word synchronized,
PN analyzer not locked
Low — Low — ¦
— High — High Ø
4 BIST running no PN mismatch this
character Low — Don’t care — ¦
— Low — Don’t care Ø