NXP Semiconductors MC92602, User Manual, Page: 4 / 48

MC92602 Reduced Interface SerDes Design Verification Board User’s Guide, Rev. 3
iv Freescale Semiconductor
Paragraph Page
Number Title Number
Chapter 3
Laboratory Equipment and Quick Setup Evaluation
3.1 Recommended Laboratory Equipment ............................................................................ 3-1
3.2 Quick Setup Data-Eye Diagram ...................................................................................... 3-2
3.2.1 Quick Setup Data-Eye Generation and Observation ................................................... 3-3
3.2.1.1 Equipment Setup...................................................................................................... 3-3
3.2.1.2 Parallel Input Connections....................................................................................... 3-4
3.2.2 Basic Eye Observation—Test Procedure..................................................................... 3-5
3.2.3 Quick Setup Bit Error Rate Checking.......................................................................... 3-6
3.2.3.1 Equipment Setup...................................................................................................... 3-6
3.2.3.2 Parallel I/O Connections.......................................................................................... 3-7
3.2.3.3 Quick Setup BERC Test Procedure ......................................................................... 3-7
Chapter 4
Test Setups
4.1 Serial Link Verification Using a Serial Bit Error Rate Tester (BERT) ............................ 4-1
4.1.1 Test Setup for Full-Speed Mode .................................................................................. 4-2
4.1.2 Test Setup for Half-Speed Mode ................................................................................. 4-2
4.2 Jitter Testing..................................................................................................................... 4-3
4.2.1 Jitter Test System Calibration ...................................................................................... 4-3
4.2.2 Reference Clock Jitter Transfer Test............................................................................ 4-4
4.2.3 Reference Clock Jitter Tolerance Test ......................................................................... 4-5
4.2.4 Data Jitter Tolerance Test............................................................................................. 4-6
Appendix A
Connector Signals
A.1 Input: 2
×
10 (0.100") Connectors.................................................................................... A-1
A.1.1 Control Signal Input Connectors ................................................................................ A-1
A.1.2 Transmitter Parallel Data Input Connectors ............................................................... A-3
A.2 Output: 2
×
20 (0.100") Connectors................................................................................. A-4
A.3 TEST_0 Connector ......................................................................................................... A-5
Appendix B
Parts List
B.1 Design Verification Board Parts List ...............................................................................B-1