NXP Semiconductors LPC5411 Series Product Data Sheet Download Page 67

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LPC5411x

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Product data sheet

Rev. 2.1 — 9 May 2018

67 of 105

NXP Semiconductors

LPC5411x

32-bit ARM Cortex-M4/M0+ microcontroller

11.7 Watchdog oscillator

[1]

Typical ratings are not guaranteed. The values listed are at nominal supply voltages.

[2]

The typical frequency spread over processing and temperature (T

amb





C to +105



C) is



40 %.

[3]

Actual jitter dependent on amplitude and spectrum of substrate noise.

[4]

Guaranteed by design. Not tested in production samples.

11.8 I

C-bus

[1]

Guaranteed by design. Not tested in production.

[2]

Parameters are valid over operating temperature range unless otherwise specified. See the I

C-bus specification

UM10204

for details.

[3]

tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.

[4]

A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V

(min) of the SCL signal) to

bridge the undefined region of the falling edge of SCL.

[5]

= total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.

Table 28.

Dynamic characteristics: Watchdog oscillator

amb





C to +105



C; 1.62 V





3.6 V

Symbol

Parameter

Min

Typ

[1]

Max

Unit

osc(int)

internal watchdog oscillator
frequency

[2]

1500

kHz

clkout

clkout duty cycle

PP-CC

peak-peak period jitter

[3][4]

start

start-up time

[4]



Table 29.

Dynamic characteristic: I

C-bus pins

[1]

amb





C to +105



C; 1.62 V



3.6 V

[2]

Symbol

Parameter

Conditions

Min

Max

Unit

SCL

SCL clock frequency

Standard-mode

100

kHz

Fast-mode

400

kHz

Fast-mode Plus

MHz

fall time

[4][5][6][7]

of both SDA and SCL signals

Standard-mode

300

Fast-mode

20 + 0.1



300

Fast-mode Plus

120

LOW

LOW period of the SCL clock

Standard-mode

4.7



Fast-mode

1.3



Fast-mode Plus

0.5



HIGH

HIGH period of the SCL clock

Standard-mode

4.0



Fast-mode

0.6



Fast-mode Plus

0.26



HD;DAT

data hold time

[3][4][8]

Standard-mode



Fast-mode



Fast-mode Plus



SU;DAT

data set-up time

[9][10]

Standard-mode

250

Fast-mode

100

Fast-mode Plus

Summary of Contents for LPC5411 Series

Page 1: ...e ARM Cortex M4 supports single cycle digital signal processing and SIMD instructions A hardware floating point unit is integrated in the core The ARM Cortex M0 coprocessor is an energy efficient and easy to use 32 bit core which is code and tool compatible with the Cortex M4 core The Cortex M0 coprocessor offers up to 100 MHz performance with a simple instruction set and reduced code size 2 Featu...

Page 2: ...ght serial peripherals Each can be selected by software to be a USART SPI or I2C interface Two Flexcomm Interfaces also include an I2S interface Each Flexcomm Interface includes a FIFO that supports USART SPI and I2S if supported by that Flexcomm Interface A variety of clocking options are available to each Flexcomm Interface and include a shared fractional baud rate generator I2C bus interfaces s...

Page 3: ...es ten events and ten states 32 bit Real time clock RTC with 1 s resolution running in the always on power domain A timer in the RTC can be used for wake up from all low power modes including deep power down with 1 ms resolution Multiple channel multi rate 24 bit timer MRT for repetitive interrupt generation at up to four programmable fixed rates Windowed Watchdog Timer WWDT Clock generation 12 MH...

Page 4: ...crocontroller The Micro Tick Timer running from the watchdog oscillator can be used to wake up the device from any reduced power modes Power On Reset POR Brown Out Detect BOD with separate thresholds for interrupt and forced reset Single power supply 1 62 V to 3 6 V JTAG boundary scan supported 128 bit unique device serial number for identification Operating temperature range 40 C to 105 C Availab...

Page 5: ...113J128BD64 LQFP64 plastic low profile quad flat package 64 leads body 10 10 1 4 mm SOT314 2 LPC54113J256BD64 LQFP64 plastic low profile quad flat package 64 leads body 10 10 1 4 mm SOT314 2 LPC54114J256BD64 LQFP64 plastic low profile quad flat package 64 leads body 10 10 1 4 mm SOT314 2 Table 2 Ordering options Type number Flash in KB SRAM in KB Cortex M4 with FPU Cortex M0 USB FS GPIO SRAMX SRAM...

Page 6: ...ash size Second line BD64 Third line xxxxxxxxxxxx Fourth line xxxyywwx R x yyww Date code with yy year and ww week xR Boot code version and device revision The LPC5411x WLCSP49 package has the following top side marking First line LPC5411x x 4 dual core M4 M0 x 3 single core M4 Second line JxxxUK49 xxx flash size Third line xxxxxxxx Fourth line xxxyyww yyww Date code with yy year and ww week Fifth...

Page 7: ... MULTILAYER AHB MATRIX I O CONFIGURATION GPIO GROUP INTERRUPTS 0 AND 1 PERIPHERAL INPUT MUXES MULTI RATE TIMER FREQUENCY MEASUREMENT UNIT PMU REGISTERS 32 BIT TIMER TIMER 2 FLASH REGISTERS FLEXCOMM Interfaces 5 THROUGH 7 1 DMIC SUBSYSTEM REGISTERS ADC 5 Ms s 12 BIT 12 ch TEMPERATURE SENSOR GPIO SCTIMER PWM FRACTIONAL RATE GENERATOR SYSTEM FUNCTIONS CLOCKING RESET POWER FLASH ETC Serial Wire Debug ...

Page 8: ...Semiconductors N V 2018 All rights reserved Product data sheet Rev 2 1 9 May 2018 8 of 105 NXP Semiconductors LPC5411x 32 bit ARM Cortex M4 M0 microcontroller 6 Pinning information 6 1 Pinning Fig 4 WLCSP49 Pin configuration ball A1 pin 1 index area A B C D E F G 7 6 5 4 3 2 1 aaa 015470 ...

Page 9: ... PIO1_9 53 SWDIO PIO0_17 28 PIO1_8 54 PIO1_13 27 PIO1_7 55 VSS 26 PIO1_6 56 VDD 25 VSS 57 PIO1_14 24 VDD 58 PIO0_18 23 VDDA 59 PIO0_19 22 VREFP 60 PIO0_20 21 VREFN 61 PIO0_21 20 VSSA 62 PIO1_15 19 PIO1_5 63 PIO0_22 18 PIO1_4 64 RESET 17 PIO1_3 1 PIO0_23 48 PIO0_13 2 PIO0_24 47 PIO0_12 3 PIO0_25 46 PIO0_11 4 PIO0_26 45 PIO0_10 5 USB_DP 44 PIO0_9 6 USB_DM 43 PIO0_8 7 PIO1_16 42 PIO1_11 8 VDD 41 PIO0...

Page 10: ...rk In ISP mode this pin is set to the Flexcomm Interface 0 USART TXD function I O FC0_TXD_SCL_MISO Flexcomm Interface 0 USART TXD I2C SCL SPI MISO I O FC3_RTS_SCL_SSEL1 Flexcomm Interface 3 USART RTS I2C SCL SPI SSEL1 I CTimer0_CAP1 32 bit CTimer0 capture input 1 R Reserved O SCT0_OUT1 SCT0 output 1 PWM output 1 PIO0_2 36 2 PU I O PIO0_2 General purpose digital input output pin I O FC0_CTS_SDA_SSE...

Page 11: ... O FC6_SCK Flexcomm Interface 6 USART SPI or I2S clock O SCT0_OUT0 SCT0 output 0 PWM output 0 O CTimer0_MAT2 32 bit CTimer0 match output 2 R Reserved I CTimer0_CAP2 32 bit CTimer0 capture input 2 PIO0_8 D5 43 2 PU I O PIO0_8 General purpose digital input output pin I O FC2_RXD_SDA_MOSI Flexcomm Interface 2 USART RXD I2C SDA SPI MOSI O SCT0_OUT1 SCT0 output 1 PWM output 1 O CTimer0_MAT3 32 bit CTim...

Page 12: ...13 G7 48 2 PU I O PIO0_13 General purpose digital input output pin In ISP mode this pin is set to the Flexcomm 3 SPI MISO function I O FC3_TXD_SCL_MISO Flexcomm Interface 3 USART TXD I2C SCL SPI MISO O SCT0_OUT4 SCT0 output 4 PWM output 4 O CTimer2_MAT0 32 bit CTimer2 match output 0 PIO0_14 TCK F6 49 2 PU I O PIO0_14 General purpose digital input output pin In boundary scan mode TCK Test Clock In ...

Page 13: ...ter booting PIO0_18 TRST G4 58 2 PU I O PIO0_18 General purpose digital input output pin In boundary scan mode TRST Test Reset I O FC5_TXD_SCL_MISO Flexcomm Interface 5 USART TXD I2C SCL SPI MISO O SCT0_OUT0 SCT0 output 0 PWM output 0 O CTimer0_MAT0 32 bit CTimer0 match output 0 PIO0_19 TDI G3 59 2 PU I O PIO0_19 General purpose digital input output pin In boundary scan mode TDI Test Data In I O F...

Page 14: ...o tick timer capture input 1 PIO0_24 F1 2 3 Z I O PIO0_24 General purpose digital input output pin In ISP mode this pin is set to the Flexcomm 1 I2C SDA function I O FC1_CTS_SDA_SSEL0 Flexcomm Interface 1 USART CTS I2C SDA SPI SSEL0 R Reserved I CTimer0_CAP1 32 bit CTimer0 capture input 1 R Reserved O CTimer0_MAT0 32 bit CTimer0 match output 0 PIO0_25 E2 3 3 Z I O PIO0_25 General purpose digital i...

Page 15: ...tput 2 R Reserved I CTimer0_CAP2 32 bit CTimer0 capture input 2 PIO0_31 ADC0_2 C2 13 4 PU I O AI PIO0_31 ADC0_2 General purpose digital input output pin ADC input channel 2 if the DIGIMODE bit is set to 0 in the IOCON register for this pin Remark This pin is also used to invoke ISP mode after device reset Secondary selection of boot source for ISP mode also uses PIO0_4 and PIO1_6 See the Boot Proc...

Page 16: ... O FC4_RXD_SDA_MOSI Flexcomm Interface 4 USART RXD I2C SDA SPI MOSI PIO1_3 ADC0_6 B2 17 4 PU I O AI PIO1_3 ADC0_6 General purpose digital input output pin ADC input channel 6 if the DIGIMODE bit is set to 0 in the IOCON register for this pin R Reserved I O FC7_SSEL2 Flexcomm Interface 7 SPI SSEL2 O SCT0_OUT6 SCT0 output 6 PWM output 6 R Reserved I O FC3_SCK Flexcomm Interface 3 USART or SPI clock ...

Page 17: ...P mode after device reset in connection with PIO0_31 and PIO0_4 See the Boot Process chapter in UM10914 for more details R Reserved I O FC7_SCK Flexcomm Interface 7 USART SPI or I2S clock I CTimer1_CAP2 32 bit CTimer1 capture input 2 R Reserved O CTimer1_MAT2 32 bit CTimer1 match output 2 R Reserved I USB_VBUS Monitors the presence of USB bus power This signal must be HIGH for USB reset to occur P...

Page 18: ...ace 6 USART TXD I2C SCL SPI MISO I2S WS O SCT0_OUT4 SCT0 output 4 PWM output 4 I O FC1_SCK Flexcomm Interface 1 USART or SPI clock R Reserved R Reserved I USB_FRAME USB start of frame signal derived from host signaling PIO1_11 42 2 PU I O PIO1_11 General purpose digital input output pin R Reserved I O FC6_RTS_SCL_SSEL1 Flexcomm Interface 6 USART RTS I2C SCL SPI SSEL1 I CTimer1_CAP0 32 bit CTimer1 ...

Page 19: ...utput 5 I CTimer1_CAP3 32 bit CTimer1 capture input 3 I O FC7_CTS_SDA_SSEL0 Flexcomm Interface 7 USART CTS I2C SDA SPI SSEL0 PIO1_16 7 2 PU I O PIO1_16 General purpose digital input output pin I PDM0_DATA Data for PDM interface 0 digital microphone input O CTimer0_MAT0 32 bit CTimer0 match output 0 I CTimer0_CAP0 32 bit CTimer0 capture input 0 I O FC7_RTS_SCL_SSEL1 Flexcomm Interface 7 USART RTS I...

Page 20: ...is from 3 ns to 16 ns simulated value 3 True open drain pin I2C bus pins compliant with the I2C bus specification for I2C standard mode I2C Fast mode and I2C Fast mode Plus The pin requires an external pull up to provide output functionality When power is switched off this pin is floating and does not disturb the I2C lines Open drain configuration applies to all functions on this pin 4 5 V toleran...

Page 21: ...Pin states in different power modes 1 Default and programmed pin states are retained in sleep and deep sleep modes Table 5 Termination of unused pins Pin Default state 1 Recommended termination of unused pins RESET I PU The RESET pin can be left unconnected if the application does not use it all PIOn_m not open drain I PU Can be left unconnected if driven LOW and configured as GPIO output with pul...

Page 22: ...estore for interrupts tightly integrated interrupt controller with wake up interrupt controller and multiple core buses capable of simultaneous accesses A 3 stage pipeline is employed so that all parts of the processing and memory systems can operate continuously Typically while one instruction is being executed its successor is being decoded and a third instruction is being fetched from memory 7 ...

Page 23: ...ex M4 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts 7 6 1 Features Controls system exceptions and peripheral interrupts 40 vectored interrupt slots Eight programmable interrupt priority levels with hardware priority level masking Relocatable vector table using Vector Table Offset Register VTOR Non Maskable Interrupt NMI Software...

Page 24: ...em clock or the SYSTICK clock 7 9 On chip static RAM The LPC5411x supports up to192 KB SRAM with separate bus master access for higher throughput and individual power control for low power operation 7 10 On chip flash The LPC5411x supports up to 256 KB of on chip flash memory 7 11 On chip ROM The 32 KB on chip ROM contains the boot loader and the following Application Programming Interfaces API In...

Page 25: ...LPC5411x 32 bit ARM Cortex M4 M0 microcontroller 7 12 Memory mapping The LPC5411x incorporates several distinct memory regions The APB peripheral area is 64 KB in size and is divided to allow for up to 32 peripherals Each peripheral is allocated 4 KB of space simplifying the address decoding Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset ...

Page 26: ...comm Interface 5 CRC engine reserved DMIC interface High Speed GPIO Mailbox Flexcomm Interface 4 Flexcomm Interface 3 Flexcomm Interface 2 Flexcomm Interface 1 APB peripherals active interrupt vectors reserved private peripheral bus 1 AHB peripherals Asynchronous APB peripherals reserved reserved reserved Boot ROM reserved peripheral bit band addressing Memory space 0xFFFF FFFF 0xE010 0000 0xE000 ...

Page 27: ...med to 1 accuracy over the entire voltage and temperature range 7 13 1 2 Watchdog oscillator WDTOSC The watchdog oscillator is a low power internal oscillator The WDTOSC can be used to provide a clock to the WWDT and to the entire chip The watchdog oscillator has a selectable frequency in the range of 6 kHz to 1 5 MHz Fig 7 LPC5411x APB Memory map 31 21 20 19 13 12 11 9 8 7 0 0x4003 FFFF 0x4003 50...

Page 28: ...d as the clock source to the main clock 7 13 1 5 System PLL The system PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency external clock The system PLL can run from the internal FRO 12 MHz output the external clock input CLKIN or the RTC oscillator The system PLL accepts an input clock frequency in the range of 32 kHz to 25 MHz The input frequency is multipli...

Page 29: ...iptions for details APB clock select B ASYNCAPBCLKSELB 1 0 Main clock select B MAINCLKSELB 1 0 000 001 010 clk_in fro_12m wdt_clk 011 32k_clk 111 none PLL clock select SYSPLLCLKSEL 2 0 FRG CLOCK DIVIDER FRGCTRL 15 0 000 001 010 pll_clk main_clk fro_12m 011 fro_hf 111 none FRG clock select FRGCLKSEL 2 0 000 001 010 fro_hf fro_12 pll_clk 011 mclk_in 100 frg_clk 111 none aaa 022102 Function clock sel...

Page 30: ...chip via the SWD and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased 2 CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands 3 CRP3 fully disables any access to the chip v...

Page 31: ...peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static 7 15 2 Deep sleep mode In deep sleep mode the system clock to the processor is disabled as in sleep mode All analog blocks are powered down by default but can be selected to keep running through the power API if needed as wake up sources The main clock and all peripheral clocks are disabled ...

Page 32: ...tandby Off BOD Software configured Software configured Off PLL Software configured Off Off Watchdog osc and WWDT Software configured Software configured Off Micro tick Timer Software configured Software configured Off DMA Active Configurable some for operations see Section 7 13 2 Off USART Software configured Off but can create a wake up interrupt in synchronous slave mode or 32 kHz clock mode Off...

Page 33: ... kHz timer time out and alarm Enable the RTC 1 Hz oscillator and the RTC 1 kHz oscillator in the RTC CTRL register Start RTC 1 kHz timer by writing a value to the WAKE register of the RTC Enable the RTC wake up interrupt in the STARTER0 register Micro tick timer intended for ultra low power wake up from deep sleep mode Enable the watchdog oscillator in the PDRUNCFG0 register Enable the Micro tick ...

Page 34: ...t bits as a group leaving other bits unchanged All GPIO registers are byte and half word addressable Entire port value can be written in one instruction Bit level set clear and toggle registers allow a single instruction set clear or toggle of any number of bits in one port Direction control of individual bits All I O default to inputs after reset All GPIO pins can be selected to create an edge or...

Page 35: ...lice minterm product term comprising of the specified boolean expression can generate its own dedicated interrupt request Any occurrence of a pattern match can also be programmed to generate an RXEV notification to the CPU The RXEV signal can be connected to a pin Pattern match can be used in conjunction with software to create complex state machines based on pin inputs Pattern match engine facili...

Page 36: ... Supports Single and double buffering Supports Crystal less operation and calibration of FRO using USB frames Each non control endpoint supports bulk interrupt or isochronous endpoint types Link Power Management LPM supported 7 19 2 DMIC subsystem 7 19 2 1 Features Pulse Density Modulation PDM data input for left and or right channels on 1 or 2 buses Flexible decimation 16 entry FIFO for each chan...

Page 37: ...mpare RS 485 transceiver output enable Autobaud mode for automatic baud rate detection Parity generation and checking odd even or none Software selectable oversampling from 5 to 16 clocks in asynchronous mode One transmit and one receive data buffer RTS CTS for hardware signaling for automatic flow control Software flow control can be performed using Delta CTS detect Transmit Disable control and a...

Page 38: ...tional Microwire modes are not supported 7 19 6 I2C bus interface The I2C bus is bidirectional for inter IC control using only two wires a serial clock line SCL and a serial data line SDA Each device is recognized by a unique address and can operate as either a receiver only device for example an LCD driver or a transmitter with the capability to both receive and send information such as memory Tr...

Page 39: ... an MCLK input and or output this is handled outside of the I2S block in the system level clocking scheme 7 19 8 1 Features A Flexcomm Interface may implement one or more I2S channel pairs the first of which could be a master or a slave and the rest of which would be slaves All channel pairs are configured together for either transmit or receive and other shared attributes The number of channel pa...

Page 40: ...n input pulse and capturing the timer value on the trailing edge Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs per timer corresponding to match registers with the following capabilities Set LOW on match ...

Page 41: ...toggle any SCTimer PWM output Force a capture of the count value into any capture registers Generate an interrupt of DMA request 7 20 2 1 Features The SCTimer PWM Supports Eight inputs Eight outputs Ten match capture registers Ten events Ten states Counter timer features Each SCTimer PWM is configurable as two 16 bit counters or one 32 bit counter Counters clocked by system clock or selected input...

Page 42: ...counter is running A state changes into another state as a result of an event Each event can be assigned to one or more states State variable allows sequencing across multiple counter cycles 7 20 3 Windowed WatchDog Timer WWDT The purpose of the Watchdog Timer is to reset or interrupt the microcontroller within a programmable time if it enters an erroneous state When enabled a watchdog reset is ge...

Page 43: ...o wake up the part from any low power modes This timer is intended to be used for timed wake up from deep sleep or deep power down modes The high resolution wake up timer can be disabled to conserve power if not used The RTC timer uses the 32 768 kHz clock input to create a 1 Hz or 1 kHz clock 7 20 4 1 Features The RTC oscillator has the following clock outputs 32 768 kHz clock selectable for syst...

Page 44: ...ally to the SCTimer PWM inputs for tight timing control between the ADC and the SCTimer PWM 7 21 1 Features 12 bit successive approximation analog to digital converter Input multiplexing up to 12 pins Two configurable conversion sequences with independent triggers Optional automatic high low threshold comparison and zero crossing detection Measurement range VREFN to VREFP not to exceed VDDA voltag...

Page 45: ...nine conversion or more burst provides an accurate result 7 23 Emulation and debugging Debug and trace functions are integrated into the ARM Cortex M4 and ARM Cortex M0 Serial wire debug and trace functions are supported The ARM Cortex M4 is configured to support up to eight breakpoints and four watch points The ARM Cortex M0 is configured to support up to four breakpoints and two watch points In ...

Page 46: ...t is limited to 25 times the corresponding maximum current 4 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 k series resistor 5 VDD present or not present Compliant with the I2C bus standard 5 5 V can be applied to this pin when VDD is powered down 6 Applies to all 5 V tolerant I O pins except true open drain pins 7 Including the voltage on outputs in 3 state mode Tabl...

Page 47: ...t on package type 9 Thermal characteristics The average chip junction temperature Tj C can be calculated using the following equation 1 Tamb ambient temperature C Rth j a the package junction to ambient thermal resistance C W PD sum of internal and I O power dissipation The internal power dissipation is the product of IDD and VDD The I O power dissipation of the I O pins is often small and many ti...

Page 48: ...ply voltages Table 12 General operating conditions Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Conditions Min Typ 1 Max Unit fclk clock frequency internal CPU system clock 100 MHz For USB full speed device operation 12 100 MHz VDD supply voltage core and external rail 1 62 3 6 V For USB operation only 3 0 3 6 V VDDA analog supply voltage 1 62 3 6 V Vrefp ADC positive reference v...

Page 49: ...ark score CoreMark code executed from SRAMX CCLK 12 MHz 1 2 3 5 6 2 6 Iterations s MHz CCLK 48 MHz 1 2 3 5 6 2 6 Iterations s MHz CCLK 96 MHz 1 2 3 5 6 2 6 Iterations s MHz CoreMark score CoreMark code executed from flash CCLK 12 MHz 1 system clock flash access time 1 2 3 4 6 2 6 Iterations s MHz CCLK 48 MHz 3 system clock flash access time 1 2 3 4 6 2 4 Iterations s MHz CCLK 96 MHz 6 system clock...

Page 50: ...sabled See the FLASHCFG register in the LPC5411x UM10914 User Manual for system clock flash access time settings Measured with Keil uVision 5 17 Optimization level 3 optimized for time ON 12 MHz 48 MHz and 96 MHz FRO enabled PLL disabled 24 MHz 36 MHz 60 MHz 72 MHz 84 MHz and 100 MHz FRO enabled PLL enabled Fig 9 Typical CoreMark score DDD UHTXHQF 0 RUHPDUN VFRUH RUHPDUN VFRUH RUHPDUN VFRUH LWHUDW...

Page 51: ...M0 and SRAMX are powered SRAM1 and SRAM2 are powered down All peripheral clocks disabled 7 Characterized using low power regulation mode Table 14 Static characteristics Power consumption in active mode Tamb 40 C to 105 C unless otherwise specified 1 62 V VDD 3 6 V Symbol Parameter Conditions Min Typ 1 Max Unit ARM Cortex M0 in active mode ARM Cortex M4 in sleep mode IDD supply current CoreMark cod...

Page 52: ...SHCFG register See the FLASHCFG register in the LPC5411x UM10914 User Manual for system clock flash access time settings SRAM0 and SRAMX powered SRAM1 and SRAM2 powered down Measured with Keil uVision 5 17 Optimization level 0 optimized for time OFF 12 MHz 48 MHz and 96 MHz FRO enabled PLL disabled 24 MHz 36 MHz 60 MHz 72 MHz 84 MHz and 100 MHz FRO enabled PLL enabled Fig 10 CoreMark power consump...

Page 53: ...oduction VDD 2 0 V Table 16 Static characteristics Power consumption in deep sleep and deep power down modes Tamb 40 C to 105 C 1 62 V VDD 2 0 V unless otherwise specified Symbol Parameter Conditions Min Typ 1 2 Max 3 Unit IDD supply current Deep sleep mode Flash is powered down SRAM0 64 KB powered Tamb 25 C 10 17 A SRAM0 64 KB powered Tamb 105 C 167 SRAM0 64 KB SRAM1 64 KB powered 13 A SRAM0 64 K...

Page 54: ...40 C to 105 C 2 7 V VDD 3 6 V unless otherwise specified Symbol Parameter Conditions Min Typ 1 2 Max 3 Unit IDD supply current Deep sleep mode Flash is powered down SRAM0 64 KB powered Tamb 25 C 12 19 A SRAM0 64 KB powered Tamb 105 C 182 SRAM0 64 KB SRAM1 64 KB powered 15 A SRAM0 64 KB SRAM1 64 KB SRAM2 32 KB powered 16 A SRAM0 64 KB SRAM1 64 KB SRAM2 32 KB SRAMX 32 KB powered 18 A Deep power down...

Page 55: ...aracterized through bench measurements using typical samples Conditions RTC disabled RTC oscillator input grounded Fig 12 Deep power down mode Typical supply current IDD versus temperature for different supply voltages VDD DDD 7HPSHUDWXUH 9 9 9 9 9 9 9 9 9 9 9 9 Table 18 Typical peripheral power consumption 1 2 3 VDD 3 3 V Tamb 25 C Peripheral IDD in uA FRO 12 MHz 48 MHz 96 MHz 100 0 WDT OSC 2 0 F...

Page 56: ...65 1 67 1 67 SCTimer PWM 4 01 4 05 4 04 Flexcomm Interface 0 USART SPI I2C 1 1 1 2 1 2 Flexcomm Interface1 USART SPI I2C 1 2 1 2 1 2 Flexcomm Interface 2 USART SPI I2C 1 2 1 2 1 2 Flexcomm Interface 3 USART SPI I2C 1 1 1 1 1 1 Flexcomm Interface 4 USART SPI I2C 1 2 1 2 1 2 Flexcomm Interface 5 USART SPI I2C 1 3 1 3 1 3 Flexcomm Interface 6 USART SPI I2C I2S 1 3 1 3 1 3 Flexcomm Interface 7 USART S...

Page 57: ...GH level input current VI VDD on chip pull down resistor disabled 3 0 180 nA VI input voltage pin configured to provide a digital function VDD 1 8 V 3 0 5 0 V VDD 0 V 0 3 6 V VIH HIGH level input voltage 1 62 V VDD 2 7 V 1 5 5 0 V 2 7 V VDD 3 6 V 2 0 5 0 V VIL LOW level input voltage 1 62 V VDD 2 7 V 0 5 0 4 V 2 7 V VDD 3 6 V 0 5 0 8 V Vhys hysteresis voltage 14 0 1 VDD V Output characteristics VO...

Page 58: ...0 A IOL LOW level output current VOL 0 4 V pin configured for standard mode or fast mode 4 0 mA VOL 0 4V pin configured for Fast mode Plus 20 mA USB_DM and USB_DP pins VI input voltage 0 VDD V VIH HIGH level input voltage 2 0 V VIL LOW level input voltage 0 8 V Vhys hysteresis voltage 0 4 V Zout output impedance 11 33 0 44 Ω VOH HIGH level output voltage 12 2 8 V VOL LOW level output voltage 13 0 ...

Page 59: ...the I O pin to the VDD level 8 The value specified is a simulated value excluding package bondwire capacitance 9 Without 33 Ω 2 series external resistor 10 The parameter values specified are simulated and absolute values 11 With 33 Ω 2 series external resistor 12 With 15 KΩ 5 resistor to VSS 13 With 1 5 KΩ 5 resistor to 3 6 V external pull up 14 Guaranteed by design not tested in production Pin ca...

Page 60: ...haracteristics Conditions VDD 1 8 V on pins PIO0_23 to PIO0_26 Conditions VDD 3 3 V on pins PIO0_23 to PIO0_26 Fig 14 I2C bus pins high current sink Typical LOW level output current IOL versus LOW level output voltage VOL DDD 92 9 2 2 2 P P P DDD 92 9 2 2 2 P P P Conditions VDD 1 8 V on standard port pins Conditions VDD 3 3 V on standard port pins Fig 15 Typical LOW level output current IOL versus...

Page 61: ...tex M4 M0 microcontroller Conditions VDD 1 8 V on standard port pins Conditions VDD 3 3 V on standard port pins Fig 16 Typical HIGH level output voltage VOH versus HIGH level output source current IOH DDD 2 P 92 2 92 9 9 9 DDD 2 P 92 2 92 9 9 9 Conditions VDD 1 8 V on standard port pins Conditions VDD 3 3 V on standard port pins Fig 17 Typical pull up current IPU versus input voltage VI DDD 9 9 SX...

Page 62: ...ll rights reserved Product data sheet Rev 2 1 9 May 2018 62 of 105 NXP Semiconductors LPC5411x 32 bit ARM Cortex M4 M0 microcontroller Conditions VDD 1 8V on standard port pins Conditions VDD 3 3 V on standard port pins Fig 18 Typical pull down current IPD versus input voltage VI DDD 9 9 SG SG SG DDD 9 9 SG SG SG ...

Page 63: ...tret retention time powered 10 years unpowered 10 years ter erase time page sector or multiple consecutive sectors 100 ms tprog programming time 3 1 ms Table 22 Dynamic characteristic I O pins 1 Tamb 40 C to 85 C unless otherwise specified 1 62 V VDD 3 6 V unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Standard I O pins normal drive strength tr rise time pin configured as ...

Page 64: ...re 25 C nominal supply voltages 2 The wake up time measured is the time between when a GPIO input pin is triggered to wake the device up from the low power modes and from when a GPIO output pin is set in the interrupt service routine ISR wake up handler 3 FRO enabled all peripherals off PLL disabled 4 RTC disabled Wake up from deep power down causes the part to go through entire reset process The ...

Page 65: ...ing lowest CCO frequency to obtain the desired output frequency Table 24 PLL lock times and current Tamb 40 C to 105 C VDD 1 62 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit PLL configuration input frequency 12 MHz output frequency 75 MHz tlock PLL PLL lock time PLL set up procedure followed 2 400 s IDD PLL PLL current when locked 1 3 550 A PLL configuration input frequency 12 MHz output...

Page 66: ...n 13 5 for connecting the RTC oscillator to an external clock source 1 Parameters are valid over operating temperature range unless otherwise specified Table 25 Dynamic characteristics of the PLL 1 Tamb 40 C to 105 C VDD 1 62 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit Reference clock input Fin input frequency 32 768 kHz 25 MHz Clock output fo output frequency for PLL clkout output 2 1...

Page 67: ...ith respect to the VIH min of the SCL signal to bridge the undefined region of the falling edge of SCL 5 Cb total capacitance of one bus line in pF If mixed with Hs mode devices faster fall times are allowed Table 28 Dynamic characteristics Watchdog oscillator Tamb 40 C to 105 C 1 62 V VDD 3 6 V Symbol Parameter Min Typ 1 Max Unit fosc int internal watchdog oscillator frequency 2 6 1500 kHz Dclkou...

Page 68: ...transmission and the acknowledge 10 A Fast mode I2C bus device can be used in a Standard mode I2C bus system but the requirement tSU DAT 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tr max tSU DAT 1000 250 125...

Page 69: ...Hz 0 0 ns CCLK 96 MHz 0 0 ns Slave 1 62 V VDD 2 0 V tv Q data output valid time on pin I2Sx_TX_SDA 2 CCLK 1 MHz to 12 MHz 25 8 47 0 ns CCLK 48 MHz to 60 MHz 23 0 38 9 ns CCLK 96 MHz 22 2 37 1 ns tsu D data input set up time on pin I2Sx_RX_SDA 2 CCLK 1 MHz to 12 MHz 0 0 ns CCLK 48 MHz to 60 MHz 0 0 ns CCLK 96 MHz 0 0 ns on pin I2Sx_RX_WS CCLK 1 MHz to 12 MHz 0 0 ns CCLK 48 MHz to 60 MHz 0 0 ns CCLK...

Page 70: ...1 7 ns CCLK 48 MHz to 60 MHz 1 4 ns CCLK 96 MHz 1 2 ns Slave 2 7 V VDD 3 6 V tv Q data output valid time on pin I2Sx_TX_SDA 2 CCLK 1 MHz to 12 MHz 17 4 33 8 ns CCLK 48 MHz to 60 MHz 15 2 25 1 ns CCLK 96 MHz 14 5 23 0 ns tsu D data input set up time on pin I2Sx_RX_SDA 2 CCLK 1 MHz to 12 MHz 0 0 ns CCLK 48 MHz to 60 MHz 0 0 ns CCLK 96 MHz 0 0 ns on pin I2Sx_RX_WS CCLK 1 MHz to 12 MHz 0 0 ns CCLK 48 ...

Page 71: ...atings are not guaranteed 4 The Flexcomm Interface function clock frequency should not be above 48 MHz See the data rates section in the I2S chapter UM10912 to calculate clock and sample rates 5 Based on simulation Not tested in production Fig 20 I2S bus timing master Fig 21 I2S bus timing slave aaa 026799 I2Sx_SCK I2Sx_TX_SDA I2Sx_WS Tcy clk tf tr tWH tWL tv Q tv Q tsu D th D I2Sx_RX_SDA aaa 0268...

Page 72: ...e rising or falling edge Symbol Parameter Conditions Min Typ 2 Max Unit SPI master 1 62 V VDD 2 0 V tDS data set up time CCLK 1 MHz to 12 MHz 0 ns CCLK 48 MHz to 60 MHz 0 ns CCLK 96 MHz 0 ns tDH data hold time CCLK 1 MHz to 12 MHz 7 ns CCLK 48 MHz to 60 MHz 7 ns CCLK 96 MHz 7 ns tv Q data output valid time CCLK 1 MHz to 12 MHz 0 5 ns CCLK 48 MHz to 60 MHz 0 3 ns CCLK 96 MHz 0 2 ns SPI slave 1 62 V...

Page 73: ... CCLK 1 MHz to 12 MHz 20 44 ns CCLK 48 MHz to 60 MHz 15 32 ns CCLK 96 MHz 13 30 ns Table 31 SPI dynamic characteristics 1 Tamb 40 C to 105 C VDD 1 62 V to 3 6 V CL 30 pF balanced loading on all pins Input slew 1 ns SLEW set to standard mode for all pins Parameters sampled at the 90 and 10 level of the rising or falling edge Symbol Parameter Conditions Min Typ 2 Max Unit Fig 22 SPI master timing SC...

Page 74: ...tex M4 M0 microcontroller Fig 23 SPI slave timing SCK CPOL 0 MISO CPHA 1 SSEL MOSI CPHA 1 Tcy clk tDS tDH tv Q DATA VALID LSB DATA VALID tv Q SCK CPOL 1 DATA VALID LSB DATA VALID MISO CPHA 0 MOSI CPHA 0 tDS tDH DATA VALID MSB DATA VALID MSB DATA VALID DATA VALID LSB DATA VALID LSB tv Q DATA VALID MSB DATA VALID tv Q aaa 014970 DATA VALID MSB DATA VALID MSB DATA VALID MSB DATA VALID MSB IDLE IDLE I...

Page 75: ... Conditions Min Typ 2 Max Unit USART master in synchronous mode 1 62 V VDD 2 0 V tsu D data input set up time CCLK 1 MHz to 12 MHz 45 ns CCLK 48 MHz to 60 MHz 39 ns CCLK 96 MHz 38 ns th D data input hold time CCLK 1 MHz to 12 MHz 0 ns CCLK 48 MHz to 60 MHz 0 ns CCLK 96 MHz 0 ns tv Q data output valid time CCLK 1 MHz to 12 MHz 2 9 ns CCLK 48 MHz to 60 MHz 1 5 ns CCLK 96 MHz 1 4 ns USART slave in sy...

Page 76: ... CCLK 1 MHz to 12 MHz 19 42 ns CCLK 48 MHz to 60 MHz 14 31 ns CCLK 96 MHz 13 28 ns Table 32 USART dynamic characteristics 1 Tamb 40 C to 105 C VDD 1 62 V to 3 6 V CL 30 pF balanced loading on all pins Input slew 1 ns SLEW set to standard mode for all pins Parameters sampled at the 90 and 10 level of the rising or falling edge Symbol Parameter Conditions Min Typ 2 Max Unit Fig 24 USART timing Un_SC...

Page 77: ...MHz 13 ns CCLK 96 MHz 9 ns tDH data hold time CCLK 1 MHz to 12 MHz 0 ns CCLK 48 MHz to 60 MHz 0 ns CCLK 96 MHz 0 ns Fig 25 DMIC timing diagram aaa 017025 CLOCK DATA tSU tDH Table 35 Dynamic characteristics USB pins Full Speed CL 50 pF Rpu 1 5 k on D to VDD unless otherwise specified 3 0 V VDD 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 to 90 4 0 20 ns tf fall time 10 to 90 4...

Page 78: ...conductors LPC5411x 32 bit ARM Cortex M4 M0 microcontroller 1 Characterized but not implemented as production test Guaranteed by design Fig 26 Differential data to EOP transition skew and EOP width 002aab561 TPERIOD differential data lines crossover point source EOP width tFEOPT receiver EOP width tEOPR1 tEOPR2 crossover point extended differential data to SE0 EOP skew n TPERIOD tFDEOP ...

Page 79: ...acterization not tested in production Symbol Parameter Conditions Min Typ Max Unit Vth threshold voltage interrupt level 0 assertion 1 97 V de assertion 2 11 V Vth threshold voltage interrupt level 1 assertion 2 36 V de assertion 2 51 V reset level 1 assertion 1 77 V de assertion 1 92 V Vth threshold voltage interrupt level 2 assertion 2 66 V de assertion 2 80 V reset level 2 assertion 1 92 V de a...

Page 80: ...t of gain and offset errors See Figure 27 7 The offset error EO is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 27 Table 37 12 bit ADC static characteristics Tamb 40 C to 105 C 1 62 V VDD 3 6 V VSSA VREFN GND ADC calibrated at Tamb 25 C Symbol Parameter Conditions Min Typ 2 Max Unit VIA analog input voltag...

Page 81: ... maximum sampling frequency fs 5 0 Msamples s and analog input capacitance Cia 5 pF 10 Input impedance Zi is inversely proportional to the sampling frequency and the total input capacity including Cia and Cio Zi 1 fs Ci See Table 20 for Cio See Figure 28 1 Example of an actual transfer curve 2 The ideal transfer curve 3 Differential linearity error ED 4 Integral non linearity EL adj 5 Center of a ...

Page 82: ..._0 fast channels ADC resolution 10 bit ts sampling time Zo 0 05 kΩ 3 15 ns 0 05 kΩ Zo 0 1 kΩ 18 ns 0 1 kΩ Zo 0 2 kΩ 20 ns 0 2 kΩ Zo 0 5 kΩ 24 ns 0 5 kΩ Zo 1 kΩ 38 ns 1 kΩ Zo 5 kΩ 62 ns ADC inputs ADC_5 to ADC_0 fast channels ADC resolution 8 bit ts sampling time Zo 0 05 kΩ 3 12 ns 0 05 kΩ Zo 0 1 kΩ 13 ns 0 1 kΩ Zo 0 2 kΩ 15 ns 0 2 kΩ Zo 0 5 kΩ 19 ns 0 5 kΩ Zo 1 kΩ 30 ns 1 kΩ Zo 5 kΩ 48 ns ADC inpu...

Page 83: ...st channels ADC inputs 0 to 5 are selected the ADC input signal goes through Rsw to the sampling capacitor Cia If slow channels ADC inputs 6 to 11 are selected the ADC input signal goes through R1 Rsw to the sampling capacitor Cia Typical values R1 487 Rsw 278 See Table 20 for Cio See Table 37 for Cia ADC inputs ADC_11 to ADC_6 slow channels ADC resolution 10 bit ts sampling time Zo 0 05 kΩ 3 35 n...

Page 84: ...erature sensor 1 Absolute temperature accuracy 2 Based on simulation Fig 28 ADC input impedance DAC ADC Rsw R1 Cia ADCx ADCy Cio Cio aaa 017600 Table 39 Temperature sensor static and dynamic characteristics VDD VDDA 1 62 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit DTsen sensor temperature accuracy Tamb 40 C to 105 C 1 3 C EL linearity error Tamb 40 C to 105 C 3 C ts pu power up settlin...

Page 85: ...ver typical samples 2 Measured for samples over process corners Table 40 Temperature sensor Linear Least Square LLS fit parameters VDD VDDA 1 62 V to 3 6 V Fit parameter Range Min Typ Max Unit LLS slope Tamb 40 C to 105 C 1 2 0 mV C LLS intercept at 0 C Tamb 40 C to 105 C 1 590 0 mV Value at 30 C 2 521 0 540 0 mV VDD VDDA 3 3 V measured on matrix samples Fig 29 LLS fit of the temperature sensor ou...

Page 86: ... reach operating voltage 13 2 Standard I O pin configuration Figure 31 shows the possible pin modes for standard I O pins Digital output driver enabled disabled Digital input Pull up enabled disabled Digital input Pull down enabled disabled Fig 30 Start up timing Table 41 Typical start up timing parameters Parameter Description Value ta FRO start time 20 s tb Internal reset de asserted 151 s tc Le...

Page 87: ... O pins is Z mode The weak MOS devices provide a drive capability equivalent to pull up and pull down resistors The glitch filter rejects pulses of typical 12 ns width Fig 31 Standard I O and RESET pin configuration aaa 017273 pin configured as digital output open drain enable output enable data output pin configured as digital input pin configured as analog input digital input analog input enable...

Page 88: ... filters the power line Tie VDDA and VREFP to VDD if the ADC is not used Tie VREFN to VSS if ADC is not used 4 Uses the ARM 10 pin interface for SWD 5 When measuring signals of low frequency use a low pass filter to remove noise and to improve ADC performance Also see Ref 1 6 External pull up resistors on SWDIO and SWCLK pins are optional because these pins have an internal pull up enabled by defa...

Page 89: ...in This current can be obtained using the parameters Ipu and Ipd given in Table 20 If pins are configured as digital outputs the static current is obtained from parameters IOH and IOL shown in Table 20 and any external load connected to the pin When an I O pin switches in an application it contributes to the dynamic power consumption because the VDD supply provides the current to charge and discha...

Page 90: ...ing the proper crystal the external load capacitor CX1 and CX2 values can also be generally determined by the following expression CX1 CX2 2CL CPad CParasitic Where CL Crystal load capacitance CPad Pad capacitance of the RTCXIN and RTCXOUT pins 3 pF CParasitic Parasitic or stray capacitance of external circuit Although CParasitic can be ignored in general the actual board layout and placement of e...

Page 91: ...B interface solutions The USB device can be connected to the USB as self powered device see Figure 34 or bus powered device see Figure 35 On the LPC5411x the USB_VBUS pin is 5 V tolerant only when VDD is applied and at operating voltage level Therefore if the USB_VBUS function is connected to the USB connector and the device is self powered the USB_VBUS pin must be protected for situations when VD...

Page 92: ...33 Ω USB R2 R3 D D Two options exist for connecting VBUS to the USB_VBUS pin 1 Connect the regulator output to USB_VBUS In this case the USB_VBUS signal is HIGH whenever the part is powered 2 Connect the VBUS signal directly from the connector to the USB_VBUS pin In this case 5 V are applied to the USB_VBUS pin while the regulator is ramping up to supply VDD Since the USB_VBUS pin is only 5 V tole...

Page 93: ...e date IEC JEDEC JEITA sot1444 5_po Unit mm max nom min 0 565 0 525 0 485 0 23 0 20 0 17 0 29 0 26 0 23 3 47 3 44 3 41 3 47 3 44 3 41 2 4 2 4 0 05 A Dimensions mm are the original dimensions A1 A2 0 350 0 325 0 300 b D E 0 03 y e 0 4 e1 e2 v 0 015 w ball A1 index area ball A1 index area X e2 e detail X C y e1 e b A C B Ø v C Ø w D 7 6 5 4 3 2 1 B D E A A A2 A1 15 01 30 16 01 20 SOT1444 5 WLCSP49 w...

Page 94: ...UE DATE IEC JEDEC JEITA mm 1 6 0 20 0 05 1 45 1 35 0 25 0 27 0 17 0 18 0 12 10 1 9 9 0 5 12 15 11 85 1 45 1 05 7 0 o o 0 12 0 1 1 0 2 DIMENSIONS mm are the original dimensions Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included 0 75 0 45 SOT314 2 MS 026 136E10 00 01 19 03 02 25 D 1 1 1 10 1 9 9 HD 12 15 11 85 E Z 1 45 1 05 D bp e θ E A1 A Lp detail X L A 3 B 16 c D H b...

Page 95: ...ment is subject to legal disclaimers NXP Semiconductors N V 2018 All rights reserved Product data sheet Rev 2 1 9 May 2018 95 of 105 NXP Semiconductors LPC5411x 32 bit ARM Cortex M4 M0 microcontroller 15 Soldering Fig 38 WLCSP49 Soldering footprint ...

Page 96: ...M0 microcontroller Fig 39 LQFP64 Soldering footprint SOT314 2 DIMENSIONS in mm occupied area Footprint information for reflow soldering of LQFP64 package Ax Bx Gx Gy Hy Hx Ay By P1 P2 D2 8x D1 0 125 Ax Ay Bx By D1 D2 Gx Gy Hx Hy 13 300 13 300 10 300 10 300 P1 0 500 P2 0 560 0 280 C 1 500 0 400 10 500 10 500 13 550 13 550 sot314 2_fr solder land C Generic footprint pattern Refer to the package outl...

Page 97: ... Advanced High performance Bus APB Advanced Peripheral Bus API Application Programming Interface CDC Communication Device Class DMA Direct Memory Access FRO oscillator Internal Free Running Oscillator tuned to the factory specified frequency GPIO General Purpose Input Output FRO Free Running Oscillator HID Human Interface Device LSB Least Significant Bit MCU MicroController Unit MSC Mass Storage D...

Page 98: ...oldering footprint Added Figure 39 LQFP64 Soldering footprint LPC5411x v 1 9 20180126 Product data sheet LPC5411x v 1 8 Modifications Updated a feature in Section 7 19 5 SPI serial I O controller Maximum data rate of 48 Mbit s in master mode and 15 Mbit s in slave mode for SPI functions Was 71 Mbit s in master mode Updated Section 11 10 SPI interfaces the maximum supported bit rate for SPI master ...

Page 99: ...chip ROM ROM based USB drivers HID CDC MSC DFU Replaced list item in ROM API support in Section 2 Features and benefits and Section 7 11 On chip ROM Legacy Single and Dual image boot Changed text in clock generation in Section 2 Features and benefits Section 7 18 3 1 Features and Section 7 21 1 2 Watchdog oscillator WDTOSC was Watchdog oscillator WDTOSC with a frequency range of 200 kHz to 1 5 MHz...

Page 100: ...functions in master mode and slave mode See Section 7 17 5 Updated Figure 8 LPC5411x clock generation Added a table note to Table 16 Static characteristics Power consumption in deep sleep and deep power down modes 3 Guaranteed by characterization not tested in production VDD 2 0 V PLL section renamed to System PLL See Section 11 4 System PLL Added Section 13 1 Start up behavior Updated Figure 31 S...

Page 101: ... 40 C to 105 C unless otherwise specified 1 62 V VDD 3 6 V to Table 15 Static characteristics Power consumption in sleep mode on page 51 Moved Figure 10 CoreMark power consumption typical mA MHz for M4 and M0 cores after Table 15 Static characteristics Power consumption in sleep mode on page 51 Updated table notes to Table 18 Typical peripheral power consumption 1 2 3 on page 54 Added Table 19 Typ...

Page 102: ...conductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability fo...

Page 103: ...ent or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b whenever customer uses the product for automotive applications beyond NXP Semiconductors specifica...

Page 104: ...13 3 Brownout detection 30 7 13 4 Safety 30 7 14 Code security Code Read Protection CRP 30 7 15 Power control 31 7 15 1 Sleep mode 31 7 15 2 Deep sleep mode 31 7 15 3 Deep power down mode 31 7 16 General Purpose I O GPIO 34 7 16 1 Features 34 7 17 Pin interrupt pattern engine 34 7 17 1 Features 35 7 18 AHB peripherals 35 7 18 1 DMA controller 35 7 18 1 1 Features 35 7 19 Digital serial peripherals...

Page 105: ...terfaces 72 11 11 USART interface 75 11 12 SCTimer PWM output timing 76 11 13 DMIC subsystem 77 11 14 USB interface characteristics 77 12 Analog characteristics 79 12 1 BOD 79 12 2 12 bit ADC characteristics 80 12 2 1 ADC input impedance 83 12 3 Temperature sensor 84 13 Application information 86 13 1 Start up behavior 86 13 2 Standard I O pin configuration 86 13 3 Connecting power clocks and debu...

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