LPC5411x
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© NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet
Rev. 2.1 — 9 May 2018
39 of 105
NXP Semiconductors
LPC5411x
32-bit ARM Cortex-M4/M0+ microcontroller
•
No chip clocks are required in order to receive and compare an address as a Slave,
so this event can wake up the device from deep-sleep mode.
7.19.8 I
2
S-bus interface
The I
2
S bus provides a standard communication interface for streaming data transfer
applications such as digital audio or data collection. The I
2
S bus specification defines a
3-wire serial bus, having one data, one clock, and one word select/frame trigger signal,
providing single or dual (mono or stereo) audio data transfer as well as other
configurations. In the LPC5411x, the I
2
S function is included in Flexcomm Interface 6 and
Flexcomm Interface 7. Each of these Flexcomm Interfaces implement four I
2
S channel
pairs.
The I
2
S interface within one Flexcomm Interface provides at least one channel pair that
can be configured as a master or a slave. Other channel pairs, if present, always operate
as slaves. All of the channel pairs within one Flexcomm Interface share one set of I
2
S
signals, and are configured together for either transmit or receive operation, using the
same mode, same data configuration and frame configuration. All such channel pairs can
participate in a time division multiplexing (TDM) arrangement. For cases requiring an
MCLK input and/or output, this is handled outside of the I
2
S block in the system level
clocking scheme.
7.19.8.1
Features
•
A Flexcomm Interface may implement one or more I
2
S channel pairs, the first of which
could be a master or a slave, and the rest of which would be slaves. All channel pairs
are configured together for either transmit or receive and other shared attributes. The
number of channel pairs is defined for each Flexcomm Interface, and may be from 0
to 4.
•
Configurable data size for all channels within one Flexcomm Interface, from 4 bits to
32 bits. Each channel pair can also be configured independently to act as a single
channel (mono as opposed to stereo operation).
•
All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and
word select/frame trigger (WS), and data line (SDA).
•
Data for all I
2
S traffic within one Flexcomm Interface uses the Flexcomm Interface
FIFO. The FIFO depth is 8 entries.
•
Left justified and right justified data modes.
•
DMA support using FIFO level triggering.
•
TDM (Time Division Multiplexing) with a several stereo slots and/or mono slots is
supported. Each channel pair can act as any data slot. Multiple channel pairs can
participate as different slots on one TDM data line.
•
The bit clock and WS can be selectively inverted.
•
Sampling frequencies supported depends on the specific device configuration and
applications constraints (e.g. system clock frequency, PLL availability, etc.) but
generally supports standard audio data rates. See the data rates section in I2S
chapter (UM10914) to calculate clock and sample rates.
Remark:
The Flexcomm Interface function clock frequency should not be above 48 MHz.
