CHAPTER 3 CPU ARCHITECTURE
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User’s Manual U11302EJ4V0UM
3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) which undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register which functions as an accumulator (A and AX) in the general-purpose register area is automatically
(implicitly) addressed.
Of the
µ
PD780208 Subseries instruction words, the following instructions employ implied addressing.
Instruction
Register to Be Specified by Implied Addressing
MULU
Register A for multiplicand and register AX for product storage
DIVUW
Register AX for dividend and quotient storage
ADJBA/ADJBS
Register A for storage of numeric values subject to decimal adjustment
ROR4/ROL4
Register A for storage of digit data which undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format
is necessary.
[Description example]
In the case of MULU X
With an 8-bit x 8-bit multiply instruction, the product of register A and register X is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
