CHAPTER 5 CLOCK GENERATOR
102
User’s Manual U11302EJ4V0UM
5.3 Clock Generator Control Registers
The clock generator is controlled by the following three registers.
• Processor clock control register (PCC)
• Display mode register 0 (DSPM0)
• Display mode register 1 (DSPM1)
(1) Processor clock control register (PCC)
PCC sets CPU clock selection, the ratio of division, main system clock oscillator operation/stop, and subsystem
clock oscillator internal feedback resistor enable/disable.
PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PCC to 04H.
Figure 5-2. Feedback Resistor of Subsystem Clock
XT1
XT2
P-ch
FRC
