CHAPTER 15 VFD CONTROLLER/DRIVER
303
User’s Manual U11302EJ4V0UM
15.3 VFD Controller/Driver Control Registers
15.3.1 Control registers
There are three registers for controlling the VFD controller/driver.
•
Display mode register 0 (DSPM0)
•
Display mode register 1 (DSPM1)
•
Display mode register 2 (DSPM2)
(1) Display mode register 0 (DSPM0) (see Figure 15-3)
This register sets the following and displays the display timing/key scan state.
• Display mode
• Display segment number/display output total number
• Mode for subsystem clock noise eliminator
DSPM0 is set with an 8-bit memory manipulation instruction. However, only bit 7 (KSF) can be read with
a 1-bit memory manipulation instruction.
RESET input sets DSPM0 to 00H.
(2) Display mode register 1 (DSPM1) (see Figure 15-4)
This register sets the following.
• Display digit number/display pattern number
• Cut width of the VFD output signal
• Display cycle (T
DSP
)
When bit 0 (DIMS0) is set to 1 and the display cycle to 2048/f
x
(409.6
µ
s: @ 5.0 MHz operation), light leakage
is reduced. As the display cycle approaches the commercial power supply frequency when the display digits
are increased, the display will flicker. In this case, select 1024/f
x
(204.8
µ
s: @ 5.0 MHz operation). If light
leaks, adjust the cut width of the digit signal using bits 1 to 3 (DIMS1 to DIMS3).
DSPM1 is set with an 8-bit memory manipulation instruction.
RESET input sets DSPM1 to 00H.
