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NEC mPD780208 Subseries, User Manual


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CHAPTER 3   CPU ARCHITECTURE

56

User’s Manual  U11302EJ4V0UM

Figure 3-7.  Data Memory Addressing (

µ

PD780205 and 

µ

PD780205A)

0000H

Internal ROM

40960 x 8 bits

Internal high-speed RAM

1024 x 8 bits

Buffer RAM

64 x 8 bits

Reserved

A000H
9FFFH

FFFFH

General-purpose registers

32 x 8 bits

Special-function registers (SFRs)

256 x 8 bits

FB00H
FAFFH

FAC0H
FABFH

FEE0H
FEDFH

FF00H
FEFFH

VFD display RAM

80 x 8 bits

FA80H
FA7FH

FA30H
FA2FH

Reserved

FF20H
FF1FH

Direct addressing

Register indirect addressing

Based addressing

Based indexed addressing

FE20H
FE1FH

SFR addressing

Register addressing

Short direct
addressing

Summary of Contents for mPD780208 Subseries

Page 1: ...series 8 Bit Single Chip Microcontrollers PD780204 PD780204A PD780205 PD780205A PD780206 PD780208 PD78P0208 Document No U11302EJ4V0UM00 4th edition Date Published July 2003 N CP K Printed in Japan Use...

Page 2: ...2 User s Manual U11302EJ4V0UM MEMO...

Page 3: ...uding work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW bo...

Page 4: ...to persons arising from defects in NEC Electronics products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC Elec...

Page 5: ...ch Seoul Korea Tel 02 558 3737 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 NEC Electronics Singapore Pte Ltd Novena Squa...

Page 6: ...EVENT COUNTER p 133 Modification of Caution in Figure 6 8 Format of External Interrupt Mode Register p 144 Modification of 6 6 5 Valid edge setting CHAPTER 8 WATCH TIMER p 171 Modification of Caution...

Page 7: ...is manual in the order of the CONTENTS For how to interpret the register format For a bit number enclosed in angle brackets the bit name is defined as a reserved word in the RA78K0 and is defined in t...

Page 8: ...U11789E CC78K0 C Compiler Operation U14297E Language U14298E SM78K Series System Simulator Ver 2 30 or Later Operation WindowsTM Based U15373E External Part User Open Interface Specification U15802E I...

Page 9: ...ucts and Packages X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Preven...

Page 10: ...1 38 2 2 3 P20 to P27 Port 2 39 2 2 4 P30 to P37 Port 3 39 2 2 5 P70 to P74 Port 7 40 2 2 6 P80 to P87 Port 8 40 2 2 7 P90 to P97 Port 9 40 2 2 8 P100 to P107 Port 10 41 2 2 9 P110 to P117 Port 11 41...

Page 11: ...essing 77 3 4 7 Based addressing 78 3 4 8 Based indexed addressing 79 3 4 9 Stack addressing 79 CHAPTER 4 PORT FUNCTIONS 80 4 1 Port Functions 80 4 2 Port Configuration 83 4 2 1 Port 0 83 4 2 2 Port 1...

Page 12: ...ration 140 6 5 5 Square wave output operation 142 6 6 16 Bit Timer Event Counter Operating Precautions 143 CHAPTER 7 8 BIT TIMER EVENT COUNTER 145 7 1 8 Bit Timer Event Counter Functions 145 7 1 1 8 b...

Page 13: ...nel 0 207 13 3 Control Registers of Serial Interface Channel 0 211 13 4 Operations of Serial Interface Channel 0 217 13 4 1 Operation stop mode 217 13 4 2 3 wire serial I O mode operation 218 13 4 3 S...

Page 14: ...icing Operations 347 16 4 1 Non maskable interrupt request acknowledgment operation 347 16 4 2 Maskable interrupt request acknowledgment operation 350 16 4 3 Software interrupt request acknowledgment...

Page 15: ...1 B 3 Control Software 402 B 4 PROM Programming Tools 403 B 4 1 Hardware 403 B 4 2 Software 403 B 5 Debugging Tools Hardware 404 B 5 1 When using in circuit emulator IE 78K0 NS IE 78K0 NS A 404 B 5 2...

Page 16: ...84 4 3 Block Diagram of P01 to P03 84 4 4 Block Diagram of P10 to P17 85 4 5 Block Diagram of P20 P21 P23 to P26 86 4 6 Block Diagram of P22 and P27 87 4 7 Block Diagram of P30 to P37 88 4 8 Block Dia...

Page 17: ...ified 140 6 17 External Event Counter Configuration Diagram 141 6 18 External Event Counter Operation Timing with Rising Edge Specified 141 6 19 Square Wave Output Operation Timing 142 6 20 16 Bit Tim...

Page 18: ...Basic Operation of A D Converter 198 12 5 Relationship Between Analog Input Voltage and A D Conversion Result 199 12 6 A D Conversion by Hardware Start 200 12 7 A D Conversion by Software Start 201 1...

Page 19: ...tic Data Transmit Receive Interval Specification Register 265 14 6 3 Wire Serial I O Mode Timing 270 14 7 Circuit for Switching Transfer Bit Order 271 14 8 Basic Transmission Reception Mode Operation...

Page 20: ...puts in 35 Segment x 16 Digit Display Mode 321 15 18 Display Data Memory Configuration and Data Reading Order Display Mode 2 322 15 19 Segment Connection Example 323 15 20 Grid Driving Timing 324 15 2...

Page 21: ...17 5 STOP Mode Release by RESET Input 366 18 1 Block Diagram of Reset Function 367 18 2 Timing of Reset by RESET Input 368 18 3 Timing of Reset due to Watchdog Timer Overflow 368 18 4 Timing of Reset...

Page 22: ...er Event Counter Square Wave Output Ranges 142 7 1 8 Bit Timer Event Counter Interval Time 146 7 2 8 Bit Timer Event Counter Square Wave Output Ranges 147 7 3 Interval Time When 8 Bit Timer Event Coun...

Page 23: ...hting Timing 324 16 1 Interrupt Source List 336 16 2 Various Flags Corresponding to Interrupt Request Sources 339 16 3 Times from Maskable Interrupt Request Generation to Interrupt Servicing 350 16 4...

Page 24: ...mum instruction execution time can be changed from high speed 0 4 s 5 0 MHz operation with main system clock to ultra low speed 122 s 32 768 kHz operation with subsystem clock 74 I O ports VFD control...

Page 25: ...QFP 14 x 20 Mask ROM PD780208GF xxx 3BA 100 pin plastic QFP 14 x 20 Mask ROM PD78P0208GF 3BA 100 pin plastic QFP 14 x 20 One time PROM Remark xxx indicates ROM code suffix 1 4 Quality Grade Part Numbe...

Page 26: ...P32 TO2 P31 TO1 P30 TO0 RESET X2 X1 IC VPP XT2 P04 XT1 VDD P27 SCK0 P26 SO0 SB1 P25 SI0 SB0 P24 BUSY P23 STB P22 SCK1 P21 SO1 P20 SI1 AVSS P17 ANI7 P16 ANI6 P15 ANI5 P14 ANI4 P13 ANI3 1 2 3 4 5 6 7 8...

Page 27: ...e power supply VPP Programming power supply VSS Ground X1 X2 Crystal main system clock XT1 XT2 Crystal subsystem clock ANI0 to ANI7 Analog input AVDD Analog power supply AVREF Analog reference voltage...

Page 28: ...le PGM Program VPP Programming power supply D0 to D7 Data bus RESET Reset VSS Ground VDD D7 D6 D5 D4 D3 D2 D1 D0 RESET Open L VPP Open L VDD A7 A6 A5 A4 A3 A2 A1 A0 VSS CE OE L D L D D 1 2 3 4 5 6 7 8...

Page 29: ...ts under development Y subseries products are compatible with I2 C bus ROMless version of the PD78078 100 pin 100 pin EMI noise reduced version of the PD78078 Inverter control PD780208 100 pin VFD dri...

Page 30: ...988 16 K to 60 K 3 ch Note 1 ch 8 ch 3 ch UART 2 ch 47 4 0 V control VFD PD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2 7 V drive PD780232 16 K to 24 K 3 ch 4 ch 40 4 5 V PD78044H 32 K to 48...

Page 31: ...rrupt control Clock output control Buzzer output TO0 P30 TI0 P00 TO1 P31 TI1 P33 TO2 P32 TI2 P34 SI0 SB0 P25 SO0 SB1 P26 SCK0 P27 SI1 P20 SO1 P21 SCK1 P22 STB P23 BUSY P24 ANI0 P10 to ANI7 P17 AVDD AV...

Page 32: ...16 pins VFD controller driver Total of display output 53 pins Segments 9 to 40 pins Digits 2 to 16 pins A D converter 8 bit resolution x 8 channels Power supply voltage AVDD 4 0 to 5 5 V Serial interf...

Page 33: ...tors and pull down resistors listed in Table 1 1 can be incorporated When these resistors are necessary the number of external components and mounting space can be saved by utilizing the mask options...

Page 34: ...ssor clock control register PCC to 1 do not use the feedback resistor contained in the subsystem clock oscillator 2 When the P10 ANI0 to P17 ANI7 pins are used as analog inputs of the A D converter se...

Page 35: ...mask option connection to VLOAD or VSS is specifiable in 4 bit units P100 to P107 I O Port 10 Input FIP29 to FIP36 P ch open drain 8 bit high withstanding voltage I O port Input output can be specifi...

Page 36: ...ock output for trimming main system clock and subsystem clock Input P35 BUZ Output Buzzer output Input P36 FIP0 to FIP12 Output High withstanding voltage and high current output for VFD controller Out...

Page 37: ...ntial IC Internally connected Connect directly to VSS 2 1 2 PROM programming mode pins PD78P0208 only Pin Name I O Function RESET Input PROM programming mode setting When 5 V or 12 5 V is applied to t...

Page 38: ...INTP0 to INTP2 are external interrupt request input pins for which valid edges can be specified rising edge falling edge and both rising and falling edges INTP0 becomes a 16 bit timer event counter c...

Page 39: ...EC Electronics standard serial bus interface I O pins d BUSY Serial interface automatic transmit receive busy input pin e STB Serial interface automatic transmit receive strobe output pin Caution If p...

Page 40: ...D controller driver Port 8 can drive LEDs directly The following operating modes can be specified in 1 bit units 1 Port mode P80 to P87 function as an 8 bit output only port P80 to P87 are P ch open d...

Page 41: ...input or output mode in 1 bit units using port mode register 11 PM11 P110 to P117 are P ch open drain outputs In mask ROM versions use of pull down resistors can be specified with the mask option 2 C...

Page 42: ...tor connection pins for subsystem clock oscillation For external clock supply input the clock to XT1 and its inverted signal to XT2 2 2 19 VDD This is the positive power supply pin 2 2 20 VSS This is...

Page 43: ...onnect to VSS P01 INTP1 8 A I O Input Independently connect to VSS via a resistor P02 INTP2 Output Leave open P03 INTP3 P04 XT1 16 Input Connect to VDD or VSS P10 ANI0 to P17 ANI7 11 I O Input Indepen...

Page 44: ...ndependently connect to VDD or VSS via a resistorNote P110 FIP37 to P117 FIP44 Output Leave open P120 FIP45 to P127 FIP52 IC Connect directly to VSS PD78P0208 P70 to P74 13 D I O Input Independently c...

Page 45: ...triggered input with hysteresis characteristics Type 5 C Type 10 A Type 8 B Type 8 A Pull up enable VDD P ch IN OUT Output disable Data VDD P ch N ch Pull up enable VDD P ch IN OUT Output disable Data...

Page 46: ...ut disable Data VDD P ch N ch P ch Comparator N ch Input enable VREF Threshold voltage VDD P ch N ch VDD P ch Data OUT VLOAD VDD P ch N ch VDD P ch Data OUT VLOAD Mask option Mask option VDD P ch N ch...

Page 47: ...r s Manual U11302EJ4V0UM Figure 2 1 Pin I O Circuits 3 3 Type 15 B Type 15 C Type 16 P ch XT2 XT1 Feedback cut off VDD P ch N ch VDD P ch Data IN OUT VLOAD Mask option Mask option RD N ch VDD P ch N c...

Page 48: ...use PD780204A C8H PD780205A CAH PD78P0208 Value corresponding to mask ROM version Figure 3 1 Memory Map PD780204 and PD780204A 0000H Data memory space Internal ROM 32768 x 8 bits 7FFFH 1000H 0FFFH 08...

Page 49: ...0040H 003FH 0000H CALLF entry area CALLT table area Program area Program area Internal high speed RAM 1024 x 8 bits Reserved Reserved Program memory space A000H 9FFFH FFFFH General purpose registers 3...

Page 50: ...ts Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits Reserved Internal ROM 49152 x 8 bits Program area CALLF entry area Program area CALLT table...

Page 51: ...ts Buffer RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits Reserved Internal ROM 61440 x 8 bits Program area CALLF entry area Program area CALLT table...

Page 52: ...table area Program area Program area Internal high speed RAM 1024 x 8 bits Reserved Reserved Program memory space F000H EFFFH FFFFH General purpose registers 32 x 8 bits Special function registers SFR...

Page 53: ...ored at even addresses and the higher 8 bits are stored at odd addresses Table 3 2 Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source 0000H RESET input 0010H INTC...

Page 54: ...area similar to the internal high speed RAM as well as a program area in which instructions can be written and executed The internal expansion RAM cannot be used as a stack memory 3 Buffer RAM Buffer...

Page 55: ...is assigned addresses FB00H to FFFFH the special function registers SFRs and general purpose registers can be addressed in accordance with thier function Data memory addressing is shown in Figures 3 6...

Page 56: ...x 8 bits Reserved A000H 9FFFH FFFFH General purpose registers 32 x 8 bits Special function registers SFRs 256 x 8 bits FB00H FAFFH FAC0H FABFH FEE0H FEDFH FF00H FEFFH VFD display RAM 80 x 8 bits FA80...

Page 57: ...RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits Reserved Internal ROM 49152 x 8 bits SFR addressing Register addressing Short direct addressing Dire...

Page 58: ...RAM 64 x 8 bits Reserved VFD display RAM 80 x 8 bits Reserved Internal expansion RAM 1024 x 8 bits Reserved Internal ROM 61440 x 8 bits SFR addressing Register addressing Short direct addressing Dire...

Page 59: ...ral purpose registers 32 x 8 bits Special function registers SFRs 256 x 8 bits FB00H FAFFH FA30H FA2FH FEE0H FEDFH FF00H FEFFH Internal expansion RAM 1024 x 8 bits F800H F7FFH F400H F3FFH Reserved FF2...

Page 60: ...neration or PUSH PSW instruction execution and are automatically reset upon execution of the RETB RETI and POP PSW instructions RESET input sets the PSW to 02H Figure 3 12 Program Status Word Format a...

Page 61: ...f Carry flag CY This flag stores overflow and underflow upon add subtract instruction execution It stores the shift out value upon rotate instruction execution and functions as a bit accumulator duri...

Page 62: ...instructions PUSH rp instruction Lower register pairs Higher register pairs SP SP 2 SP 2 SP 1 SP SP SP 2 SP 2 SP 1 SP PC7 to PC0 PC15 to PC8 SP SP 3 SP 3 SP 2 SP 1 PC15 to PC8 PSW SP PC7 to PC0 RETI a...

Page 63: ...and HL and absolute names R0 to R7 and RP0 to RP3 Register banks to be used for instruction execution are set using the CPU control instruction SEL RBn Because of the 4 register bank configuration an...

Page 64: ...ssembler for the 8 bit manipulation instruction operand sfr This manipulation can also be specified with an address 16 bit manipulation Describe the symbol reserved in the assembler for the 16 bit man...

Page 65: ...TM2 FF1AH Serial I O shift register 0 SIO0 R W Undefined FF1BH Serial I O shift register 1 SIO1 FF1FH A D conversion result register ADCR R FF20H Port mode register 0 PM0 R W 1FH FF21H Port mode regi...

Page 66: ...s pointer ADTP FF6BH Automatic data transmit receive interval specification ADTI register FF80H A D converter mode register ADM 01H FF84H A D converter input select register ADIS 00H FFA0H Display mod...

Page 67: ...clock control register PCC Note The value after resetting the internal memory size switching register IMS and internal expansion RAM size switching register IXS depends on the product PD780204 PD78020...

Page 68: ...12326E 3 3 1 Relative addressing Function The value obtained by adding 8 bit immediate data displacement value jdisp8 of an instruction code to the start address of the following instruction is transf...

Page 69: ...the CALL addr16 or BR addr16 or CALLF addr11 instruction is executed CALL addr16 and BR addr16 instructions can branch to all the memory spaces CALLF addr11 instruction branches to the area from 0800...

Page 70: ...code are transferred to the program counter PC and branched Table indirect addressing is carried out when the CALLT addr5 instruction is executed This instruction can refer to the address stored in t...

Page 71: ...4 Register addressing Function Register pair AX contents to be specified with an instruction word are transferred to the program counter PC and branched This function is carried out when the BR AX in...

Page 72: ...nstruction Register to Be Specified by Implied Addressing MULU Register A for multiplicand and register AX for product storage DIVUW Register AX for dividend and quotient storage ADJBA ADJBS Register...

Page 73: ...he following operand format is executed When an 8 bit register is specified one of the eight registers is specified with 3 bits in the operation code Operand format Identifier Description r X A C B E...

Page 74: ...data in an instruction word is directly addressed Operand format Identifier Description addr16 Label or 16 bit immediate data Description example MOV A 0FE00H when setting addr16 to FE00H Illustratio...

Page 75: ...sters of the timer event counter are mapped and these SFRs can be manipulated with a small number of bytes and clocks When 8 bit immediate data is at 20H to FFH bit 8 of an effective address is set to...

Page 76: ...to FFCFH and FFE0H to FFFFH However the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing Operand format Identifier Description sfr Special function register name sfrp 16 bit...

Page 77: ...register bank select flag RBS0 and RBS1 and the register pair specification code in the instruction code This addressing can be carried out for all the memory spaces Operand format Identifier Descript...

Page 78: ...ter pair to be accessed is in the register bank specified with the register bank select flags RBS0 and RBS1 Addition is performed by expanding the offset data as a positive number to 16 bits A carry f...

Page 79: ...its A carry from the 16th bit is ignored This addressing can be carried out for all the memory spaces Operand format Identifier Description HL B HL C Description example In the case of MOV A HL B sele...

Page 80: ...the port configuration Every port is capable of 1 bit and 8 bit manipulations and can carry out various control operations Besides port functions the ports can also serve as on chip hardware I O pins...

Page 81: ...n directly In mask ROM versions use of pull down resistors can be specified in 1 bit units with the mask option can be specified as connected to VLOAD or VSS in 4 bit units P90 to P97 Port 9 FIP21 to...

Page 82: ...0 to P117 Port 11 FIP37 to FIP44 P ch open drain 8 bit high withstanding voltage I O port Input output can be specified in 1 bit units LEDs can be driven directly In mask ROM versions use of pull down...

Page 83: ...put mode output mode in 1 bit units using port mode register 0 PM0 The P00 and P04 pins are input only port pins When the P01 to P03 pins are used as input port pins on chip pull up resistors can be c...

Page 84: ...re 4 3 Block Diagram of P01 to P03 PUO Pull up resistor option register PM Port mode register RD Port 0 read signal WR Port 0 write signal P00 INTP0 TI0 P04 XT1 RD Internal bus P ch WRPM WRPORT RD WRP...

Page 85: ...its using the pull up resistor option register PUO Alternate functions include A D converter analog input RESET input sets port 1 to input mode Figure 4 4 shows a block diagram of port 1 Caution A pul...

Page 86: ...block diagrams of port 2 Cautions 1 If used as serial interface pins set the I O and output latch according to each function Refer to Figure 13 3 Format of Serial Operating Mode Register 0 and Figure...

Page 87: ...4 6 Block Diagram of P22 and P27 PUO Pull up resistor option register PM Port mode register RD Port 2 read signal WR Port 2 write signal P ch WRPM WRPORT RD WRPUO VDD P22 SCK1 P27 SCK0 Selector PUO2...

Page 88: ...n 1 bit units with the mask option The PD78P0208 does not contain pull down resistors Port 3 can drive LEDs directly Alternate functions include timer I O clock output and buzzer output RESET input se...

Page 89: ...varies depending on the following conditions For mask ROM version When a pull up resistor is connected 3 A max regardless of operational conditions When a pull up resistor is not connected 200 A max d...

Page 90: ...s directly Alternate functions include VFD controller driver display output RESET input sets port 8 to output mode Figure 4 9 shows a block diagram of port 8 Caution Adjust the number of pull down res...

Page 91: ...directly Alternate functions include VFD controller driver display output RESET input sets port 9 to output mode Figure 4 10 shows a block diagram of port 9 Caution Adjust the number of pull down res...

Page 92: ...tors Port 10 can drive LEDs directly Alternate functions include VFD controller driver display output RESET input sets port 10 to input mode Figure 4 11 shows a block diagram of port 10 Caution Adjust...

Page 93: ...tors Port 11 can drive LEDs directly Alternate functions include VFD controller driver display output RESET input sets port 11 to input mode Figure 4 12 shows a block diagram of port 11 Caution Adjust...

Page 94: ...tors Port 12 can drive LEDs directly Alternate functions include VFD controller driver display output RESET input sets port 12 to input mode Figure 4 13 shows a block diagram of port 12 Caution Adjust...

Page 95: ...therefore the interrupt mask flag should be set to 1 beforehand Table 4 3 Port Mode Register and Output Latch Setting When Alternate Function Is Used Pin Name Alternate Function PMxx Pxx Pin Name Alt...

Page 96: ...21 PM36 PM35 PM34 PM33 PM32 PM31 PM17 PM10 PM27 PM3 PM20 PM30 PM12 PMmn Pmn pin I O mode selection m 0 1 2 3 7 10 11 12 n 0 to 7 0 1 Output mode output buffer on Input mode output buffer off FF20H FF2...

Page 97: ...s cannot be used regardless of the PUO register setting PUO is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets this register to 00H Cautions 1 The P00 and P04 pins do not in...

Page 98: ...pins the output latch contents for pins specified as input are undefined except for the manipulated bit 4 4 2 Reading from I O port 1 Output mode The output latch contents are read by a transfer instr...

Page 99: ...in 1 bit units Can incorporate pull down resistors in 1 bit units Can incorporate pull down resistors in 1 bit units The pull down resistors can be specified to be connected to VLOAD or VSS in 4 bit u...

Page 100: ...lates at a frequency of 32 768 kHz Oscillation cannot be stopped If the subsystem clock oscillator is not used the internal feedback resistor can be disabled by the processor clock control register PC...

Page 101: ...XT XT2 XT1 P04 FRC Selector Clock output function Main system clock oscillator X2 X1 fX STOP MCC FRC CLS CSS PCC2 PCC1 PCC0 Processor clock control register Internal bus Standby controller CPU clock f...

Page 102: ...register 0 DSPM0 Display mode register 1 DSPM1 1 Processor clock control register PCC PCC sets CPU clock selection the ratio of division main system clock oscillator operation stop and subsystem cloc...

Page 103: ...pulled up to VDD Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency PCC0 PCC 7 6 5 4 3 2 Symbol 1 0 CSS CPU clock fCPU selection FFFBH PCC1 0 PCC2 CSS CLS...

Page 104: ...0 8 s fX 22 1 6 s fX 23 3 2 s fX 24 6 4 s fXT 2 122 s fX 5 0 MHz fXT 32 768 kHz fX Main system clock oscillation frequency fXT Subsystem clock oscillation frequency 2 Display mode register 0 DSPM0 Thi...

Page 105: ...9 19 0 1 0 1 1 20 20 0 1 1 0 0 21 21 0 1 1 0 1 22 22 0 1 1 1 0 23 23 0 1 1 1 1 24 24 1 0 0 0 0 25 25 1 0 0 0 1 26 26 1 0 0 1 0 27 27 1 0 0 1 1 28 28 1 0 1 0 0 29 29 1 0 1 0 1 30 30 1 0 1 1 0 31 31 1 0...

Page 106: ...scan timing Notes 1 Bit 7 KSF is a read only bit 2 Set this bit according to the main system clock oscillation frequency fX selected The noise eliminator operates during VFD display 3 When fX is used...

Page 107: ...egister to set display operation stop DSPM1 is set with an 8 bit memory manipulation instruction RESET input sets DSPM1 to 00H Remark In addition to setting display operation stop DSPM1 can also set t...

Page 108: ...ped static display Note 0 0 0 1 2 digits 2 patterns 0 0 1 0 3 digits 3 patterns 0 0 1 1 4 digits 4 patterns 0 1 0 0 5 digits 5 patterns 0 1 0 1 6 digits 6 patterns 0 1 1 0 7 digits 7 patterns 0 1 1 1...

Page 109: ...ts inverted signal to the X2 pin Figure 5 6 shows an external circuit of the main system clock oscillator Figure 5 6 External Circuit of Main System Clock Oscillator a Crystal or ceramic oscillation b...

Page 110: ...illator wire as follows in the area enclosed by the broken lines in Figures 5 6 and 5 7 to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the...

Page 111: ...c High alternating current close to d Current flowing through ground line signal lines of oscillator potentials at points A B and C change Remark When using a subsystem clock replace X1 and X2 with X...

Page 112: ...lock replace X1 and X2 with XT1 and XT2 respectively Further insert resistors in series on the side of XT2 Cautions 2 If XT2 and X1 are wired in parallel malfunction may occur due to the crosstalk noi...

Page 113: ...tion operations and clock operations connect the XT1 and XT2 pins as follows XT1 Connect to VDD or VSS XT2 Leave open In this state however some current may leak via the internal feedback resistor of...

Page 114: ...system clock selected two standby modes the STOP and HALT modes are available When the system is not using the subsystem clock the power consumption in the STOP mode can be decreased if the internal f...

Page 115: ...bit 7 MCC of PCC is set to 1 during operation with the main system clock the main system clock oscillation does not stop When bit 4 CSS of PCC is set to 1 and the operation is switched to subsystem cl...

Page 116: ...en bit 5 CLS of the processor clock control register PCC is set to 1 the following operations are carried out a The minimum instruction execution time remains constant 122 s during operation at 32 768...

Page 117: ...ycle division ratio PCC0 to PCC2 and switchover from the subsystem clock to the main system clock changing CSS from 1 to 0 Remarks 1 One instruction is the minimum instruction execution time with the...

Page 118: ...s the processor clock control register PCC is rewritten and the maximum speed operation is carried out 3 Upon detection of a decrease of the VDD voltage due to an interrupt request signal the main sys...

Page 119: ...with any selected frequency Two 8 bit timer event counters can be used as one 16 bit timer event counter refer to CHAPTER 7 8 BIT TIMER EVENT COUNTER 3 Watch timer TM3 This timer can set a flag every...

Page 120: ...unction Timer output PWM output Pulse width measurement Square wave output Interrupt request Test input Notes 1 The watch timer can perform both watch timer and interval timer functions at the same ti...

Page 121: ...fX 5 0 MHz 2 PWM output TM0 can generate 14 bit resolution PWM output 3 Pulse width measurement TM0 can measure the pulse width of an externally input signal 4 External event counter TM0 can measure t...

Page 122: ...iguration Timer register 16 bits x 1 TM0 Registers 16 bit compare register 1 CR00 16 bit capture register 1 CR01 Timer outputs 1 TO0 Control registers Timer clock select register 0 TCL0 16 bit timer m...

Page 123: ...us 16 bit timer mode control register Timer clock select register 0 TCL06 TCL05 TCL04 16 bit capture register CR01 TMC03 OVF0 TMC02 TMC01 Selector f X TI0 P00 INTP0 Note 1 INTP0 16 bit timer register...

Page 124: ...the dotted line is the output controller f X 2 3 f X 2 2 f X 2 f X Internal bus Timer clock select register 0 TCL06 TCL05 TCL04 16 bit capture register CR01 16 bit timer register TM0 PWM pulse genera...

Page 125: ...l interrupt mode register INTM0 2 Bit 0 of port mode register 3 PM3 Remark The circuitry enclosed by the dotted line is the output controller TO0 P30 P30 output latch PM30 Note 2 TOE0 Selector TMC01 t...

Page 126: ...an that of the 16 bit timer register TM0 TM0 continues to count and overflows then resumes counting from 0 Therefore if the value after CR00 is changed is smaller than the value before CR00 is changed...

Page 127: ...timer output control register TOC0 Port mode register 3 PM3 External interrupt mode register INTM0 Sampling clock select register SCS 1 Timer clock select register 0 TCL0 This register is used to set...

Page 128: ...lock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3 TI0 16 bit timer event counter input pin 4 TM0 16 bit timer register 5 Figures in parentheses apply to operation with fX 5 0 MH...

Page 129: ...de the 16 bit timer register clear mode and output timing and detects an overflow TMC0 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets TMC0 to 00H Caution The 16 bit time...

Page 130: ...e Match between TM0 and 1 1 0 CR00 Match between TM0 and CR00 or TI0 valid edge Cautions 1 Switch the clear mode and the TO0 output timing after stopping the timer operation by setting TMC01 to TMC03...

Page 131: ...16 Bit Timer Output Control Register Cautions 1 Timer operation must be stopped before setting TOC0 2 If LVS0 and LVR0 are read after data is set they will be 0 TOE0 TOC0 7 6 5 4 3 2 Symbol 1 0 TOE0 1...

Page 132: ...tput set PM30 and the output latch of P30 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 6 7 Format of Port Mode Register 3 PM3 6 5 4 3 2 Symb...

Page 133: ...1 ES30 ES31 1 1 ES10 0 1 0 1 Setting prohibited Both falling and rising edges ES21 INTP1 valid edge selection 0 0 Falling edge Rising edge 1 1 ES20 0 1 0 1 Setting prohibited Both falling and rising e...

Page 134: ...9 Format of Sampling Clock Select Register Caution fX 2N 1 is the clock supplied to the CPU and fX 26 and fX 27 are clocks supplied to peripheral hardware fX 2N 1 is stopped in HALT mode Remarks 1 N V...

Page 135: ...er register TM0 matches the value set to CR00 counting continues with the TM0 value cleared to 0 and the interrupt request signal INTTM0 is generated CR00 should be set to a value other than 0000H The...

Page 136: ...16 x 1 fX 13 1 ms 1 fX 200 ns 0 1 0 22 x 1 fX 800 ns 217 x 1 fX 26 2 ms 2 x 1 fX 400 ns 0 1 1 23 x 1 fX 1 6 s 218 x 1 fX 52 4 ms 22 x 1 fX 800 ns 1 0 0 24 x 1 fX 3 2 s 219 x 1 fX 104 9 ms 23 x 1 fX 1...

Page 137: ...4 so that the time constant of the external LPF can be shortened Count clock can be selected using bits 4 to 6 TCL04 to TCL06 of timer clock select register 0 TCL0 PWM output enable disable can be sel...

Page 138: ...l input to the TI0 P00 pin 1 Pulse width measurement in free running mode When the 16 bit timer register TM0 is operated in free running mode if the edge specified by the external interrupt mode regis...

Page 139: ...g of Pulse Width Measurement Operation in Free Running Mode with Both Edges Specified 16 bit timer register TM0 fX fX 2 fX 22 fX 23 OVF0 Selector TI0 P00 INTP0 16 bit capture register CR01 INTP0 Inter...

Page 140: ...nt Operation by Means of Restart with Both Edges Specified 6 5 4 External event counter operation The external event counter counts the number of external clock pulses input to the TI0 P00 pin using t...

Page 141: ...gram Figure 6 18 External Event Counter Operation Timing with Rising Edge Specified TI0 pin input TM0 count value CR00 INTTM0 0000 0001 0002 0003 0004 0005 N _ 1 N N 0000 0001 0002 0003 16 bit compare...

Page 142: ...Width Maximum Pulse Width Resolution 0 0 0 2 x TI0 input cycle 216 x TI0 input cycle TI0 input edge cycle 0 0 1 2 x 1 fX 400 ns 216 x 1 fX 13 1 ms 1 fX 200 ns 0 1 0 22 x 1 fX 800 ns 217 x 1 fX 26 2 ms...

Page 143: ...compare register as an event counter a one pulse count operation cannot be carried out 3 Operation after compare register change during timer count operation If the value after the 16 bit compare regi...

Page 144: ...re Register Data Retention Timing 5 Valid edge setting When using the INTP0 TI0 P00 pin as a timer input pin TI0 stop the operation of the 16 bit timer by clearing bits 1 to 3 TMC01 to TMC03 of the 16...

Page 145: ...e PD780208 Subseries 8 bit timer event counter mode Two channel 8 bit timer event counter with each channel used separately 16 bit timer event counter mode Two channel 8 bit timer event counter used a...

Page 146: ...11 x 1 fX 409 6 s 23 x 1 fX 1 6 s 24 x 1 fX 3 2 s 212 x 1 fX 819 2 s 24 x 1 fX 3 2 s 25 x 1 fX 6 4 s 213 x 1 fX 1 64 ms 25 x 1 fX 6 4 s 26 x 1 fX 12 8 s 214 x 1 fX 3 28 ms 26 x 1 fX 12 8 s 27 x 1 fX 2...

Page 147: ...fX 204 8 s 22 x 1 fX 800 ns 23 x 1 fX 1 6 s 211 x 1 fX 409 6 s 23 x 1 fX 1 6 s 24 x 1 fX 3 2 s 212 x 1 fX 819 2 s 24 x 1 fX 3 2 s 25 x 1 fX 6 4 s 213 x 1 fX 1 64 ms 25 x 1 fX 6 4 s 26 x 1 fX 12 8 s 2...

Page 148: ...fX 52 4 ms 22 x 1 fX 800 ns 23 x 1 fX 1 6 s 219 x 1 fX 104 9 ms 23 x 1 fX 1 6 s 24 x 1 fX 3 2 s 220 x 1 fX 209 7 ms 24 x 1 fX 3 2 s 25 x 1 fX 6 4 s 221 x 1 fX 419 4 ms 25 x 1 fX 6 4 s 26 x 1 fX 12 8...

Page 149: ...22 x 1 fX 800 ns 218 x 1 fX 52 4 ms 22 x 1 fX 800 ns 23 x 1 fX 1 6 s 219 x 1 fX 104 9 ms 23 x 1 fX 1 6 s 24 x 1 fX 3 2 s 220 x 1 fX 209 7 ms 24 x 1 fX 3 2 s 25 x 1 fX 6 4 s 221 x 1 fX 419 4 ms 25 x 1...

Page 150: ...7 5 8 Bit Timer Event Counter Configuration Item Configuration Timer register 8 bits x 2 TM1 TM2 Registers 8 bit compare register 2 CR10 CR20 Timer outputs 2 TO1 TO2 Control registers Timer clock sel...

Page 151: ...er event counter output controller 2 TO2 P32 INTTM2 TO1 P31 Note 8 bit timer event counter output controller 1 8 bit compare register CR10 8 bit timer register 1 TM1 Match Clear Selector Selector Sele...

Page 152: ...Counter Output Controller 2 Note Bit 2 of port mode register 3 PM3 Remarks 1 The circuitry enclosed by the dotted line is the output controller 2 fSCK Serial clock frequency Figure 7 2 Block Diagram...

Page 153: ...ller than those of the 8 bit timer registers TM1 TM2 TM1 and TM2 continue to count When they overflow counting starts again from 0 Therefore it is necessary to restart the timer after changing the val...

Page 154: ...t R W 00H R W 0 TI1 falling edge 0 TI1 rising edge 0 fX 2 2 5 MHz 0 fX 2 2 1 25 MHz 0 fX 2 3 625 kHz 1 fX 2 4 313 kHz 1 fX 25 156 kHz 1 fX 26 78 1 kHz 1 fX 27 39 1 kHz 1 fX 28 19 5 kHz 1 fX 2 9 9 8 kH...

Page 155: ...gister Cautions 1 Switch the operating mode after stopping timer operation 2 When used as 16 bit timer register TMS TCE1 should be used for operation enable stop 7 6 5 4 3 2 1 0 0 0 0 0 0 TMC12 TCE2 T...

Page 156: ...2 TOC15 TOE2 LVS1 LVR1 TOC11 TOE1 Symbol TOC1 Address FF4FH After reset 00H R W R W TOE1 0 1 8 bit timer event counter 1 output control Output disabled port mode Output enabled TOC11 0 1 8 bit timer e...

Page 157: ...ut set PM31 PM32 and the output latches of P31 and P32 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 7 7 Format of Port Mode Register 3 7 6 5...

Page 158: ...h the TM1 and TM2 values cleared to 0 and interrupt request signals INTTM1 and INTTM2 are generated The count clock of TM1 can be selected using bits 0 to 3 TCL10 to TCL13 of timer clock select regist...

Page 159: ...e Setting prohibited Remarks 1 fX Main system clock oscillation frequency 2 Figures in parentheses apply to operation with fX 5 0 MHz Table 7 7 8 Bit Timer Event Counter 2 Interval Time TCL17 TCL16 TC...

Page 160: ...time the valid edge specified by timer clock select register 1 TCL1 is input Either the rising or falling edge can be selected When the TM1 and TM2 count values match the values of the 8 bit compare r...

Page 161: ...fX 1 6 s 211 x 1 fX 409 6 s 23 x 1 fX 1 6 s 1 0 0 0 24 x 1 fX 3 2 s 212 x 1 fX 819 2 s 24 x 1 fX 3 2 s 1 0 0 1 25 x 1 fX 6 4 s 213 x 1 fX 1 64 ms 25 x 1 fX 6 4 s 1 0 1 0 26 x 1 fX 12 8 s 214 x 1 fX 3...

Page 162: ...tting a count value set the value of the higher 8 bits to CR20 and the value of the lower 8 bits to CR10 For the count value interval time that can be set refer to Table 7 9 When the 8 bit timer regis...

Page 163: ...ut cycle 28 x TI1 input cycle TI1 input edge cycle 0 0 0 1 TI1 input cycle 28 x TI1 input cycle TI1 input edge cycle 0 1 0 1 2 x 1 fX 400 ns 217 x 1 fX 26 2 ms 2 x 1 fX 400 ns 0 1 1 0 22 x 1 fX 800 ns...

Page 164: ...the 8 bit compare registers CR10 and CR20 both TM1 and TM2 are cleared to 0 and the interrupt request signal INTTM2 is generated Figure 7 12 External Event Counter Operation Timing with Rising Edge S...

Page 165: ...400 ns 217 x 1 fX 26 2 ms 2 x 1 fX 400 ns 0 1 1 0 22 x 1 fX 800 ns 218 x 1 fX 52 4 ms 22 x 1 fX 800 ns 0 1 1 1 23 x 1 fX 1 6 s 219 x 1 fX 104 9 ms 23 x 1 fX 1 6 s 1 0 0 0 24 x 1 fX 3 2 s 220 x 1 fX 2...

Page 166: ...registers 1 and 2 settings The 8 bit compare registers CR10 and CR20 can be set to 00H Thus when an 8 bit compare register is used as an event counter a one pulse count operation can be carried out Wh...

Page 167: ...ose of the 8 bit timer registers TM1 and TM2 TM1 and TM2 continue counting overflow and then restart counting from 0 Thus if the value after CR10 and CR20 M change is smaller than that before the chan...

Page 168: ...tion 0 5 second intervals cannot be generated with the 5 0 MHz main system clock Switch to the 32 768 kHz subsystem clock to generate 0 5 second intervals 2 Interval timer Interrupt requests INTTM3 ar...

Page 169: ...gister TMC2 8 3 Watch Timer Control Registers The following two registers are used to control the watch timer Timer clock select register 2 TCL2 Watch timer mode control register TMC2 1 Timer clock se...

Page 170: ...nal bus INTWT INTTM3 f X 2 8 f XT f W Selector TCL24 Timer clock select register 2 Watch timer mode control register TMC21 Clear Prescaler Selector Selector 3 TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20...

Page 171: ...ion with fX 5 0 MHz or fXT 32 768 kHz TCL20 TCL2 7 6 5 4 3 2 Symbol 1 0 TCL22 Count clock selection FF42H TCL21 0 TCL22 TCL24 TCL25 TCL26 TCL27 Address After reset R W 00H R W Watchdog timer mode 0 fX...

Page 172: ...on instruction RESET input sets TMC2 to 00H Figure 8 3 Format of Watch Timer Mode Control Register 7 6 5 4 3 2 1 0 0 TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20 Symbol TMC2 Address FF4AH After reset 00H...

Page 173: ...by setting TMC22 to 1 again after setting TMC22 to 0 maximum error 26 2 ms when operated at 5 0 MHz 8 4 2 Interval timer operation The watch timer operates as an interval timer that generates interru...

Page 174: ...Timer Program Loop Detection Time Program Loop When Operated at Program Loop When Operated at Detection Time fX 5 0 MHz Detection Time fX 5 0 MHz 211 x 1 fX 410 s 215 x 1 fX 6 55 ms 212 x 1 fX 819 s...

Page 175: ...11302EJ4V0UM 9 2 Watchdog Timer Configuration The watchdog timer consists of the following hardware Table 9 3 Watchdog Timer Configuration Item Configuration Control registers Timer clock select regis...

Page 176: ...Selector 8 bit counter TCL22 TCL21 TCL20 Internal bus Timer clock select register 2 Watchdog timer mode register 3 2 2 2 3 2 4 2 5 2 6 2 8 f WDT 2 WDTM4 RUN WDTM3 RUN Controller Internal bus TMIF4 TMM...

Page 177: ...Timer clock select register 2 TCL2 Watchdog timer mode register WDTM 1 Timer clock select register 2 TCL2 This register sets the watchdog timer count clock TCL2 is set with an 8 bit memory manipulati...

Page 178: ...32 768 kHz TCL20 TCL2 7 6 5 4 3 2 Symbol 1 0 TCL22 Count clock selection FF42H TCL21 0 TCL22 TCL24 TCL25 TCL26 TCL27 Address After reset R W 00H R W Watchdog timer mode 0 fX 2 3 625 kHz 0 fX 2 4 313 k...

Page 179: ...time is up to 0 5 shorter than the time set by timer clock select register 2 TCL2 2 When using watchdog timer mode 1 and 2 make sure that the interrupt request flag TMIF4 is set to 0 before setting W...

Page 180: ...loop detection time elapses a system reset or a non maskable interrupt request is generated according to the value of WDTM bit 3 WDTM3 The watchdog timer continues operating in the HALT mode but it s...

Page 181: ...requests INTWDT has the highest default priority The interval timer continues operating in the HALT mode but it stops in the STOP mode Thus set RUN to 1 before the STOP mode is set clear the interval...

Page 182: ...put clock pulses 1 Select the clock pulse output frequency with clock pulse output disabled using bits 0 to 3 TCL00 to TCL03 of TCL0 2 Set the P35 output latch to 0 3 Set bit 5 PM35 of port mode regis...

Page 183: ...egisters The following two registers are used to control the clock output function Timer clock select register 0 TCL0 Port mode register 3 PM3 1 Timer clock select register 0 TCL0 This register sets t...

Page 184: ...Remarks 1 fX Main system clock oscillation frequency 2 fXT Subsystem clock oscillation frequency 3 TI0 16 bit timer event counter input pin 4 TM0 16 bit timer register 5 Figures in parentheses apply t...

Page 185: ...ut set PM35 and the output latch of P35 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 10 4 Format of Port Mode Register 3 7 6 5 4 3 2 1 0 PM3...

Page 186: ...CL2 2 Set the P36 output latch to 0 3 Set bit 6 PM36 of port mode register 3 PM3 to 0 set to output mode Caution Buzzer output cannot be used when the P36 output latch is set to 1 11 2 Buzzer Output C...

Page 187: ...output function Timer clock select register 2 TCL2 Port mode register 3 PM3 1 Timer clock select register 2 TCL2 This register sets the buzzer output frequency TCL2 is set with an 8 bit memory manipu...

Page 188: ...ock oscillation frequency 3 x don t care 4 Figures in parentheses apply to operation with fX 5 0 MHz or fXT 32 768 kHz TCL20 TCL2 7 6 5 4 3 2 Symbol 1 0 TCL22 Count clock selection FF42H TCL21 0 TCL22...

Page 189: ...put set PM36 and the output latch of P36 to 0 PM3 is set with a 1 bit or 8 bit memory manipulation instruction RESET input sets PM3 to FFH Figure 11 3 Format of Port Mode Register 3 7 6 5 4 3 2 1 0 PM...

Page 190: ...mode register ADM Select one channel of analog input from ANI0 to ANI7 and carry out A D conversion In the case of a hardware start when A D conversion finishes the A D converter stops and an interru...

Page 191: ...ANI3 P13 ANI4 P14 ANI5 P15 ANI6 P16 ANI7 P17 A D converter input select register 4 3 ADM1 to ADM3 Sample hold circuit Successive approximation register SAR Tap selector Voltage comparator AVREF AVSS A...

Page 192: ...istor string is connected between AVREF and AVSS and generates a voltage to be compared with the analog input 6 ANI0 to ANI7 pins These are 8 channel analog input pins used to input the analog signals...

Page 193: ...pin and the AVSS pin Therefore if the output impedance of the reference voltage source is high this will result in series connection to the series resistor string between the AVREF pin and the AVSS p...

Page 194: ...the A D converter A D converter mode register ADM A D converter input select register ADIS 1 A D converter mode register ADM This register sets the analog input channel for A D conversion conversion...

Page 195: ...nal trigger hardware start mode CS A D conversion operation control 0 Operation stop 1 Operation start Notes 1 Set so that the A D conversion time is 19 1 s or more 2 Setting prohibited because the A...

Page 196: ...re set to analog input using ADIS 2 No internal pull up resistor can be connected to the channels set to analog input using ADIS irrespective of the value of bit 1 PUO1 of the pull up resistor option...

Page 197: ...or string voltage tap and analog input is compared by the voltage comparator If the analog input is larger than 1 2 AVREF the MSB of the SAR remains set If the input is smaller than 1 2 AVREF the MSB...

Page 198: ...s reset 0 by software If a write to ADM is performed during an A D conversion operation the conversion operation is initialized and if CS is set 1 conversion starts again from the beginning RESET inpu...

Page 199: ...EF or AVREF AVREF ADCR 0 5 VIN ADCR 0 5 256 256 Remark INT Function which returns the integer part of the value in parentheses VIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion resu...

Page 200: ...tage applied to the analog input pins specified by bits 1 to 3 ADM1 to ADM3 of ADM At the end of A D conversion the conversion result is stored in the A D conversion result register ADCR and the inter...

Page 201: ...started and terminated the next A D conversion operation starts immediately A D conversion continues repeatedly until new data is written to ADM If data with CS set to 1 is written to ADM again during...

Page 202: ...his time this current must be cut in order to minimize the overall system power consumption In this example the power consumption can be reduced if a low level is output to the output port in the stan...

Page 203: ...ed as analog inputs should be set to the input mode When A D conversion is performed with any of pins ANI0 to ANI7 selected be sure not to execute an instruction that inputs data to port 1 while conve...

Page 204: ...Figure 12 10 When A D conversion is stopped ADIF must be cleared before restarting Figure 12 10 A D Conversion End Interrupt Request Generation Timing Remark n 0 1 7 m 0 1 7 7 AVDD pin The AVDD pin is...

Page 205: ...e start bit Automatic transmit receive function Transfer end flag Serial transfer end interrupt Serial transfer end interrupt request flag CSIIF0 request flag CSIIF1 SBI serial bus interface Use possi...

Page 206: ...onsumption can be reduced Input and output lines are independent and they can transfer receive at the same time so the data transfer processing time is short The start bit of 8 bit data to undergo ser...

Page 207: ...rface Channel 0 Item Configuration Registers Serial I O shift register 0 SIO0 Slave address register SVA Control registers Timer clock select register 3 TCL3 Serial operating mode register 0 CSIM0 Ser...

Page 208: ...M27 Selector P25 output latch P26 output latch CLD P27 output latch Internal bus BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT Internal bus Slave address register SVA Serial I O shift register 0 SIO0 Bus re...

Page 209: ...ared by the address comparator If they match the slave device has been selected In that case bit 6 COI of serial operating mode register 0 CSIM0 becomes 1 Address comparison can also be executed on th...

Page 210: ...ift register 0 SIO0 value matches the slave address register SVA value after address reception Note WUP is the wakeup function specification bit It is bit 5 of serial operating mode register 0 CSIM0 T...

Page 211: ...ory manipulation instruction RESET input sets TCL3 to 88H Remark Besides setting the serial clock of serial interface channel 0 TCL3 sets the serial clock of serial interface channel 1 2 Serial operat...

Page 212: ...lection FF43H TCL31 TCL33 TCL32 TCL34 TCL35 TCL36 TCL37 Address After reset R W 88H R W 0 fX 22 1 25 MHz 0 fX 2 3 625 kHz 1 fX 24 313 kHz 1 fX 2 5 156 kHz 1 fX 26 78 1 kHz 1 fX 27 39 1 kHz 1 fX 28 19...

Page 213: ...26 1 0 0 0 1 N ch open drain CMOS I O I O R W WUP Wakeup function controlNote 4 0 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generation when the...

Page 214: ...itions RELD 1 When transfer start instruction is executed When bus release signal REL is detected If SIO0 and SVA values do not match in address reception When CSIE0 0 When RESET input is applied R CM...

Page 215: ...ACKD Acknowledge detection Clear conditions ACKD 0 Set conditions ACKD 1 At the falling edge of SCK0 immediately after the When acknowledge signal ACK is detected at the busy mode has been released wh...

Page 216: ...set SIC to 0 3 When CSIE0 0 CLD becomes 0 Caution Be sure to set bits 0 to 3 to 0 Remark SVA Slave address register CSIIF0 Interrupt request flag for INTCSI0 CSIE0 Bit 7 of serial operating mode regi...

Page 217: ...hift register 0 SIO0 does not carry out shift operations and can be used as an ordinary 8 bit register In the operation stop mode the P25 SI0 SB0 P26 SO0 SB1 and P27 SCK0 pins can be used as ordinary...

Page 218: ...te a clocked serial interface Communication is carried out using three lines a serial clock SCK0 serial output SO0 and serial input SI0 1 Register setting The 3 wire serial I O mode is set by serial o...

Page 219: ...nterrupt request signal generation when the address received after bus release when CMDD RELD 1 matches the 1 slave address register SVA in SBI mode R COI Slave address comparison result flagNote 4 0...

Page 220: ...1 the SO latch is set to 1 After SO latch setting RELT is automatically cleared to 0 RELT Also cleared to 0 when CSIE0 0 R W When CMDT 1 the SO latch is cleared to 0 After SO latch clearance CMDT is...

Page 221: ...on termination of 8 bit transfer SIO0 operation stops automatically and the interrupt request flag CSIIF0 is set Figure 13 6 3 Wire Serial I O Mode Timing The SO0 pin is used for CMOS output and gener...

Page 222: ...As shown in the figure the MSB LSB can be read written in reverse form MSB LSB switching as the start bit can be specified using bit 2 CSIM02 of serial operating mode register 0 CSIM0 Figure 13 8 Cir...

Page 223: ...two or more devices using two signal lines Thus when configuring a serial bus with two or more microcontrollers or peripheral ICs the number of ports to be used and the number of wires on the board c...

Page 224: ...r CPU slave CPU a pull up resistor is necessary for the serial clock line SCK0 as well because serial clock line SCK0 input output switching is carried out asynchronously between the master and slave...

Page 225: ...are described below a Address command data identification function Serial data is distinguished into addresses commands and data b Chip select function by address transmission The master executes sla...

Page 226: ...line indicates the READY status The bus release signal and the command signal are output by the master device BUSY is output by the slave ACK can be output by either the master or slave device normall...

Page 227: ...release signal even while data is being transmitted Care should therefore be taken in the wiring b Command signal CMD The command signal is identified when the SB0 SB1 line has changed from high leve...

Page 228: ...hardware and whether or not the 8 bit data matches the slave s own specification number slave address is checked by hardware If the 8 bit data matches the slave address the slave device has been sele...

Page 229: ...on Figure 13 15 Commands Figure 13 16 Data 8 bit data following a command signal is defined as command data 8 bit data without a command signal is defined as data Command and data operation procedures...

Page 230: ...roken line indicates the READY status The acknowledge signal is a one shot pulse generated at the falling edge of SCK0 after 8 bit data transfer It can be positioned anywhere and can be synchronized w...

Page 231: ...device It is set reset at the falling edge of SCK0 When the BUSY signal is reset the master device automatically terminates the output of the SCK0 serial clock When the BUSY signal is reset and the RE...

Page 232: ...mode refer to 13 4 4 2 wire serial I O mode operation R W WUP Wakeup function controlNote 3 0 Interrupt request signal generation with each serial transfer in any mode Interrupt request signal generat...

Page 233: ...do not match in address reception When CSIE0 0 When RESET input is applied R CMDD Command detection Clear conditions CMDD 0 Set conditions CMDD 1 When transfer start instruction is executed When comm...

Page 234: ...R ACKD Acknowledge detection Clear conditions ACKD 0 Set conditions ACKD 1 At the falling edge of SCK0 immediately after the When acknowledge signal ACK is detected at the busy mode has been released...

Page 235: ...to 0 Remark SVA Slave address register CSIIF0 Interrupt request flag for INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R W...

Page 236: ...the signals in SBI Figure 13 19 RELT CMDT RELD and CMDD Operations Master Figure 13 20 RELD and CMDD Operations Slave SCK0 SB0 SB1 RELT CMDT CMDD RELD SIO0 Slave address write to SIO0 transfer start...

Page 237: ...ser s Manual U11302EJ4V0UM Figure 13 21 ACKT Operation Caution Do not set ACKT before termination of transfer SCK0 6 SB0 SB1 ACKT 7 8 9 D2 D1 D0 ACK When set during this period ACK signal is output fo...

Page 238: ...cleared during this period and ACKE 0 at the falling edge of SCK0 ACK signal is not output D2 D1 D0 SCK0 SB0 SB1 ACKE 1 2 7 8 9 D7 D6 D2 D1 D0 When ACKE 0 at this point ACK signal is not output SCK0...

Page 239: ...structed during BUSY Figure 13 24 BSYE Operation SCK0 SB0 SB1 BSYE 7 8 9 ACK 6 When BSYE 1 at this point BUSY If reset during this period and BSYE 0 at the falling edge of SCK0 D2 D1 D0 SCK0 SB0 SB1 A...

Page 240: ...1 1 ACKE 1 2 ACKT set ACKD set CMD signal is output to indicate that transmit data is an address Completion of reception Serial receive disabled because of processing Serial receive enabled i Transmi...

Page 241: ...CMD signals When CSIE0 1 execution of instruction for data write to SIO0 serial transfer start instruction Note 2 Timing of signal output to serial data bus Address value of slave device on the seria...

Page 242: ...rain output an external pull up resistor is necessary Figure 13 25 Pin Configuration Caution Because the N ch open drain output must be high impedance at the time of data reception write FFH to serial...

Page 243: ...B1 status being transmitted is fetched into the destination device that is serial I O shift register 0 SIO0 Thus transmit errors can be detected in the following two ways a Comparison of SIO0 data bef...

Page 244: ...sion INTCSI0 generation ACKD set SCK0 stop Hardware operation WUP 0 ACKT set Program processing CMDD set INTCSI0 generation ACK output Hardware operation CMDT set RELT set CMDT set Write to SIO0 Inter...

Page 245: ...g Serial transmission INTCSI0 generation ACKD set SCK0 stop Hardware operation ACKT set Program processing INTCSI0 generation ACK output Hardware operation CMDT set Write to SIO0 Interrupt servicing p...

Page 246: ...Program processing Serial transmission INTCSI0 generation ACKD set SCK0 stop Hardware operation ACKT set Program processing INTCSI0 generation ACK output Hardware operation Write to SIO0 Interrupt se...

Page 247: ...reception INTCSI0 generation ACK output Serial reception Hardware operation Program processing INTCSI0 generation ACKD set Hardware operation FFH write to SIO0 Master device processing receiver Trans...

Page 248: ...0 RELT of the serial bus interface control register SBIC to 1 3 Reset the P25 and P26 output latches from 1 to 0 10 Judging busy status of slave When the device is in the master mode follow the proced...

Page 249: ...he changing timing of the bus fluctuates because of substrate capacitance etc it may be recognized as a bus release signal or a command signal even while data is being transmitted Care should therefor...

Page 250: ...ain I O I O 1 1 Note 2 Note 2 SB0 P26 1 0 0 0 1 N ch open drain CMOS I O I O R W WUP Wakeup function controlNote 3 0 Interrupt request signal generation with each serial transfer in any mode Interrupt...

Page 251: ...1 the SO latch is set to 1 After SO latch setting RELT is automatically cleared to 0 RELT Also cleared to 0 when CSIE0 0 R W When CMDT 1 the SO latch is cleared to 0 After SO latch clearance CMDT is...

Page 252: ...ss register CSIIF0 Interrupt request flag for INTCSI0 CSIE0 Bit 7 of serial operating mode register 0 CSIM0 6 5 4 3 2 1 0 7 Symbol SINT 0 CLD SIC SVAM 0 0 0 0 FF63H 00H R WNote 1 Address After reset R...

Page 253: ...ops automatically and the interrupt request flag CSIIF0 is set Figure 13 31 2 Wire Serial I O Mode Timing The SB0 SB1 pin specified for the serial data bus is an N ch open drain I O and thus it must b...

Page 254: ...s set 5 Error detection In the 2 wire serial I O mode the serial bus SB0 SB1 status being transmitted is fetched into serial I O shift register 0 SIO0 of the transmitting device Thus transmit errors c...

Page 255: ...it 1 CMDT of the serial bus interface control register SBIC The SCK0 P27 pin output manipulation procedure is described below 1 Set serial operating mode register 0 CSIM0 SCK0 pin enabled for serial o...

Page 256: ...ried out Power consumption can be reduced Input and output lines are independent and they can transfer receive at the same time so the data transfer processing time is short The start bit of 8 bit dat...

Page 257: ...tion Registers Serial I O shift register 1 SIO1 Automatic data transmit receive address pointer ADTP Control registers Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Automat...

Page 258: ...tic data transmit receive interval specification register ADTI 2 ADTI 1 ADTI 0 5 bit counter Serial I O shift register 1 SIO1 Hand shake Serial clock counter Selector SI1 P20 SO1 P21 PM21 STB P23 PM23...

Page 259: ...1 RESET input makes SIO1 undefined Caution Do not write data to SIO1 while the automatic transmit receive function is activated 2 Automatic data transmit receive address pointer ADTP This register sto...

Page 260: ...rial Interface Channel 1 The following four registers are used to control serial interface channel 1 Timer clock select register 3 TCL3 Serial operating mode register 1 CSIM1 Automatic data transmit r...

Page 261: ...tion frequency 2 Figures in parentheses apply to operation with fX 5 0 MHz TCL30 TCL3 7 6 5 4 3 2 Symbol 1 0 TCL33 Serial interface channel 0 serial clock selection FF43H TCL31 TCL33 TCL32 TCL34 TCL35...

Page 262: ...20 P21 P22 0 CMOS I O CMOS I O CMOS I O Operation enable Count operation SI1Note 3 SO1 SCK1 0 1 Note 3 Note 3 input CMOS output input 1 1 0 0 SCK1 1 0 1 CMOS output Notes 1 If external clock input has...

Page 263: ...DTC This register sets automatic receive enable disable the operating mode strobe output enable disable busy input enable disable error check enable disable and displays automatic transmit receive exe...

Page 264: ...e low BUSY0 0 1 STRB 0 1 Strobe output control Strobe output disabled Strobe output enabled TRF 1 Status of automatic transmit receive functionNote 2 Detection of termination of automatic transmission...

Page 265: ...Note 2 MaximumNote 2 0 0 0 0 0 36 8 s 0 5 fSCK 40 0 s 1 5 fSCK 0 0 0 0 1 62 4 s 0 5 fSCK 65 6 s 1 5 fSCK 0 0 0 1 0 88 0 s 0 5 fSCK 91 2 s 1 5 fSCK 0 0 0 1 1 113 6 s 0 5 fSCK 116 8 s 1 5 fSCK 0 0 1 0 0...

Page 266: ...e following expression is smaller than 2 fSCK the minimum interval time is 2 fSCK 27 56 0 5 Minimum n 1 fX fX fSCK 27 72 1 5 Maximum n 1 fX fX fSCK Cautions 1 ADTI should not be written to during oper...

Page 267: ...53 6 s 0 5 fSCK 756 8 s 1 5 fSCK 1 1 1 0 1 779 2 s 0 5 fSCK 782 4 s 1 5 fSCK 1 1 1 1 0 804 8 s 0 5 fSCK 808 0 s 1 5 fSCK 1 1 1 1 1 830 4 s 0 5 fSCK 833 6 s 1 5 fSCK Note The data transfer interval inc...

Page 268: ...output latch 14 4 Operations of Serial Interface Channel 1 The following three operating modes are available for serial interface channel 1 Operation stop mode 3 wire serial I O mode 3 wire serial I...

Page 269: ...ire serial I O mode 1 3 wire serial I O mode with automatic transmit receive function DIR Start bit SI1 pin function SO1 pin function 0 MSB SI1 P20 input SO1 CMOS output 1 LSB CSIM Shift register Seri...

Page 270: ...the serial clock SCK1 The transmit data is held in the SO1 latch and is output from the SO1 pin The receive data input to the SI1 pin is latched into SIO1 at the rising edge of SCK1 Upon termination o...

Page 271: ...Shift register 1 SIO1 Read write gate SO1 SCK1 D Q SO1 latch Start bit switching is realized by switching the bit order for data write to SIO1 The SIO1 shift order remains unchanged Thus switching bet...

Page 272: ...and the set number of bytes of data can be received and stored in the RAM Handshake signals STB and BUSY are supported by hardware to transmit receive data continuously An OSD On Screen Display LSI a...

Page 273: ...1 LSB CSIM Shift register Serial clock counter SI1 P20 SO1 P21 SCK1 P22 CSIE1 PM20 P20 PM21 P21 PM22 P22 11 1 operation operation control pin function pin function pin function Note 2 Note 2 Note 2 N...

Page 274: ...t using busy input Busy input enabled active high Busy input enabled active low BUSY0 x 0 1 STRB 0 1 Strobe output control Strobe output disabled Strobe output enabled TRF 1 Status of automatic transm...

Page 275: ...fSCK 40 0 s 1 5 fSCK 0 0 0 0 1 62 4 s 0 5 fSCK 65 6 s 1 5 fSCK 0 0 0 1 0 88 0 s 0 5 fSCK 91 2 s 1 5 fSCK 0 0 0 1 1 113 6 s 0 5 fSCK 116 8 s 1 5 fSCK 0 0 1 0 0 139 2 s 0 5 fSCK 142 4 s 1 5 fSCK 0 0 1 0...

Page 276: ...e following expression is smaller than 2 fSCK the minimum interval time is 2 fSCK 27 56 0 5 Minimum n 1 fX fX fSCK 27 72 1 5 Maximum n 1 fX fX fSCK Cautions 1 ADTI should not be written to during oper...

Page 277: ...9 2 s 0 5 fSCK 782 4 s 1 5 fSCK 1 1 1 1 0 804 8 s 0 5 fSCK 808 0 s 1 5 fSCK 1 1 1 1 1 830 4 s 0 5 fSCK 833 6 s 1 5 fSCK Note The data transfer interval includes an error The data transfer minimum and...

Page 278: ...e automatic data transmit receive interval specification register ADTI 4 Write any value to serial I O shift register 1 SIO1 transfer start trigger Caution Writing any value to SIO1 orders the start o...

Page 279: ...ic transmission reception mode operation timing and Figure 14 9 shows the operation flowchart The operation of the buffer RAM to transmit receive 6 byte data is shown in Figure 14 10 Figure 14 8 Basic...

Page 280: ...smit receive control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission rec...

Page 281: ...ii 4th byte transmission reception point refer to Figure 14 10 b Transmission reception of the third byte is completed and transmit data 4 T4 is transferred from the buffer RAM to SIO1 When transmissi...

Page 282: ...e transmission reception point c Completion of transmission reception Receive data 1 R1 Receive data 2 R2 Receive data 3 R3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FAFFH FAC5H FAC0H R...

Page 283: ...he basic transmission mode operation timing and Figure 14 12 shows the operation flowchart The operation of the buffer RAM to transmit 6 byte data in transmission mode is shown in Figure 14 13 Figure...

Page 284: ...he automatic data transmit receive control register ADTC Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Se...

Page 285: ...it data 2 T2 is transferred from the buffer RAM to SIO1 ii 4th byte transmission point refer to Figure 14 13 b Transmission of the third byte is completed and transmit data 4 T4 is transferred from th...

Page 286: ...h byte transmission point c Completion of transmission Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FAFFH FAC5H FAC0H SIO1 0 CSIIF1...

Page 287: ...are not performed the P20 SI1 P23 STB and P24 BUSY pins can be used as normal I O ports The repeat transmission mode operation timing is shown in Figure 14 14 and the operation flowchart in Figure 14...

Page 288: ...r SIO1 Serial I O shift register 1 Start Write transmit data in buffer RAM Set ADTP to the value pointer value obtained by subtracting 1 from the number of transmit data bytes Set the transmission rec...

Page 289: ...d from the buffer RAM to SIO1 ii Upon completion of transmission of 6 bytes refer to Figure 14 16 b When transmission of the sixth byte is completed the interrupt request flag CSIIF1 is not set The fi...

Page 290: ...etion of transmission of 6 bytes c 7th byte transmission point Transmit data 1 T1 Transmit data 2 T2 Transmit data 3 T3 Transmit data 4 T4 Transmit data 5 T5 Transmit data 6 T6 FAFFH FAC5H FAC0H SIO1...

Page 291: ...et to the port mode To resume automatic transmission reception set CSIE1 to 1 and write any value to serial I O shift register 1 SIO1 This enables transmission of the remaining data Cautions 1 If the...

Page 292: ...eries Slave device The master device inputs the busy signal output by the slave device to the BUSY P24 pin It samples the input busy signal in synchronization with the fall of the serial clock Even if...

Page 293: ...that because the busy signal is asynchronous to the serial clock it takes the master device up to 1 clock to sample the busy signal even if the slave device has made the busy signal inactive In addit...

Page 294: ...C to 1 Usually the busy control and strobe control options are simultaneously used for handshaking In this case the strobe signal is output from the STB P23 pin and the BUSY P24 pin is sampled While a...

Page 295: ...to a wait state The master samples the busy signal in synchronization with the fall of the serial clock If bit slippage does not occur the busy signal is found to be inactive after it has been sampled...

Page 296: ...dge and the value set in the automatic data transmit receive interval specification register ADTI Whether or not the interval depends on ADTI can be selected by setting bit 7 ADTI7 of ADTI When ADTI7...

Page 297: ...ive Interval Specification Register Table 14 3 Interval Determined by CPU Processing with Internal Clock Operation CPU Processing Interval When using multiplication instruction MAX 2 5TSCK 13TCPU When...

Page 298: ...tion is performed using an external clock the clock must be selected so that the interval is longer than the values shown below Table 14 4 Interval Determined by CPU Processing with External Clock Ope...

Page 299: ...nly pins 5 Luminance can be adjusted in 8 levels using display mode register 1 DSPM1 6 Incorporates hardware for key scan application Generates interrupt signal INTKS indicating key scan timing Output...

Page 300: ...y cycle TCYT TDSP x Displayed digits 1 TDIG Pulse width of digit signal Can be selected from 8 types using DSPM1 Note The user can select the cut width of the segment signals by setting bits 1 to 3 DI...

Page 301: ...1 Relationship Between Display Output Pins and Port Pins Display Pin Name Alternate Port Name I O FIP13 P80 For output port to to FIP20 P87 FIP21 P90 For output port to to FIP28 P97 FIP29 P100 I O po...

Page 302: ...0 DSPM0 0 0 USEG5 USEG4 USEG3 USEG2 USEG1 USEG0 DIGS3 DIGS2 DIGS1 DIGS0 DIMS3 DIMS2 DIMS1 DIMS0 KSF DSPM06 DSPM05 SEGS4 SEGS3 SEGS2 SEGS1 SEGS0 5 4 3 5 Display data memory Write mask controller Displ...

Page 303: ...struction However only bit 7 KSF can be read with a 1 bit memory manipulation instruction RESET input sets DSPM0 to 00H 2 Display mode register 1 DSPM1 see Figure 15 4 This register sets the following...

Page 304: ...he display output area defined by bits 0 to 4 of DSPM0 DSPM2 is set with an 8 bit memory manipulation instruction RESET input sets DSPM2 to 00H The following illustration shows the status of the displ...

Page 305: ...0 1 0 19 19 0 1 0 1 1 20 20 0 1 1 0 0 21 21 0 1 1 0 1 22 22 0 1 1 1 0 23 23 0 1 1 1 1 24 24 1 0 0 0 0 25 25 1 0 0 0 1 26 26 1 0 0 1 0 27 27 1 0 0 1 1 28 28 1 0 1 0 0 29 29 1 0 1 0 1 30 30 1 0 1 1 0 3...

Page 306: ...1 Key scan timing Notes 1 Bit 7 KSF is a read only bit 2 Set the values according to the main system clock oscillation frequency fX used The noise eliminator is enabled during VFD display operations 3...

Page 307: ...splay stopped static display Note 0 0 0 1 2 digits 2 patterns 0 0 1 0 3 digits 3 patterns 0 0 1 1 4 digits 4 patterns 0 1 0 0 5 digits 5 patterns 0 1 0 1 6 digits 6 patterns 0 1 1 0 7 digits 7 pattern...

Page 308: ...0 0 0 1 1 1 7 0 0 1 0 0 0 8 0 0 1 0 0 1 9 0 0 1 0 1 0 10 0 0 1 0 1 1 11 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 0 0 1 1 1 1 15 0 1 0 0 0 0 16 0 1 0 0 0 1 17 0 1 0 0 1 0 18 0 1 0 0 1 1 19 0 1 0 1...

Page 309: ...SEG3 USEG2 USEG1 USEG0 Number of mask bits to be written 1 0 0 0 0 0 32 1 0 0 0 0 1 33 1 0 0 0 1 0 34 1 0 0 0 1 1 35 1 0 0 1 0 0 36 1 0 0 1 0 1 37 1 0 0 1 1 0 38 1 0 0 1 1 1 39 Other than the above Se...

Page 310: ...cle 1024 fx 204 8 s 5 0 MHz operation or 2048 fx 409 6 s 5 0 MHz operation TKS Key scan timing TKS TDSP TDIG Pulse width of digit signal Can be selected from 8 types using DSPM1 Note The user can sele...

Page 311: ...VFD controller driver depends on the display mode set Figure 15 8 Selection of Display Mode Number of digits selected 9 2 3 4 5 6 7 8 0 10 14 11 12 13 15 16 Number of segments selected 0 9 10 11 12 13...

Page 312: ...IP26 P95 FIP27 P96 FIP28 P97 FIP29 P100 FIP30 P101 FIP31 P102 FIP51 P126 FIP52 P127 FIP0 FIP1 FIP2 FIP3 FIP4 FIP5 FIP6 FIP7 FIP8 FIP9 FIP10 FIP11 FIP12 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93...

Page 313: ...P52 P127 Figure 15 10 Relationship Between Display Data Memory Contents and Segment Output Bit 7 0 7 0 7 0 7 0 7 0 Display data memory Timing output S39 S32 S31 S24 S23 S16 S15 S8 S7 S0 FA70H FA71H FA...

Page 314: ...ritten By testing the KSF it can be determined if it is during the key scan timing and if the data input using keys is correct 15 7 2 Key scan data The data stored in ports 8 9 10 11 and 12 are output...

Page 315: ...2 as there is capacitance between the grid and segment of the VFD the timing signal pin voltage will be increased via CSG when the segment signal turns on As shown in Figure 15 13 when this voltage ex...

Page 316: ...s due to CSG varies The fewer the number of digits displayed the easier it is for light to leak Lowering the luminance of the display is also effective Figure 15 12 Light Leakage due to CSG EK Cut off...

Page 317: ...2 DSPM05 1 The following figures show VFD display examples for each display type 1 Segment type 10 segments x 11 digits 2 Dot type 35 segments x 16 digits 3 Display type in which a segment spans two...

Page 318: ...A68H FA69H FA6AH FA6BH FA6CH FA6DH FA6EH FA6FH FA50H FA51H FA52H FA53H FA54H FA55H FA56H FA57H FA58H FA59H FA5AH FA5BH FA5CH FA5DH FA5EH FA5FH FA40H FA41H FA42H FA43H FA44H FA45H FA46H FA47H FA48H FA4...

Page 319: ...0 1 0 0 0 1 1 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 FA70H FA6...

Page 320: ...T15 TKS FA70H 1 FA71H 6 FA72H FA73H FA74H FA75H FA76H FA77H FA78H FA79H FA7AH FA7BH FA7CH FA7DH FA7EH FA7FH FA60H 2 FA61H FA62H FA63H FA64H FA65H FA66H FA67H FA68H FA69H FA6AH FA6BH FA6CH FA6DH FA6EH...

Page 321: ...1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0...

Page 322: ...play mode 2 are for display patterns Therefore designate bits 4 to 7 DIGS0 to DIGS3 of display mode register 1 DSPM1 as 7 patterns and bits 0 to 4 SEGS0 to SEGS4 of display mode register 0 DSPM0 as 28...

Page 323: ...1g 1d r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 1G 300 250 200 150 100 q P23 r1 P22 r2 j _ j _ P21 q _ h _ h P20 r8 n _ n _ P19 r9 o _ o _ P18 r10 p _ p _ P17 _ _ 2a _ 2a P16 _ _ 2b _ 2b P15 _ _ 2f...

Page 324: ...ing timing must be T5 in Figure 15 20 because the Fast segment spans the 4G and 5G grids In addition it can be seen from Figure 15 3 that the Fast segment that is i segment which spans 4G and 5G can b...

Page 325: ...0 0 0 FA6 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 FA5 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0...

Page 326: ...igure 15 22 Allowable Total Power Dissipation PT TA 40 to 85 C The following example assumes the case where the display examples shown in 15 9 are displayed 15 10 1 Segment type display mode 1 DSPM05...

Page 327: ...h No of grids 1 0 4 V 3 mA 31 dots 1 1 2 9 mW 11 grids 1 16 3 Pull down resistor power dissipation Grid VOD VLOAD 2 No of grids Digit width 1 Cut width Pull down resistor value No of grids 1 5 5 V 2 V...

Page 328: ...THU FRI SAT 1 2 3 4 5 6 7 8 9 10 0 i S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 a b c d e f g h i j 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 1 1 0 1...

Page 329: ...power dissipation Grid VDD VOD Total current value of each grid Digit width 1 Cut width No of grids 1 2 V 15 mA 16 grids 1 1 26 5 mW 16 grids 1 16 Segment VDD VOD Total segment current value of illum...

Page 330: ...16 grids 1 16 Segment VOD VLOAD 2 No of illuminated dots Digit width 1 Cut width Pull down resistor value No of grids 1 5 5 V 0 4 V 35 V 2 110 dots 1 1 390 2 mW 25 k 16 grids 1 16 Total power dissipa...

Page 331: ...0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 1 1 0 1 0...

Page 332: ...power dissipation 5 5 V 21 6 mA 118 8 mW 2 Output pin power dissipation VDD VOD Total current value of each grid Digit width 1 Cut width No of grids 1 2 V 15 mA 9 grids 1 1 31 6 mW 7 grids 1 16 3 Pull...

Page 333: ...CHAPTER 15 VFD CONTROLLER DRIVER 333 User s Manual U11302EJ4V0UM 5G 4G 3G 2G 1G 1 display cycle T1 T0 T2 T3 T4 T5 T6 T0 Key scan timing Figure 15 25 Grid Driving Timing...

Page 334: ...1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 FA6 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 FA5 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0...

Page 335: ...Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag register PR0L and PR0H Multiple interrupt servici...

Page 336: ...D 3 INTP2 000AH 4 INTP3 000CH 5 INTCSI0 End of serial interface channel 0 transfer Internal 000EH B 6 INTCSI1 End of serial interface channel 1 transfer 0010H 7 INTTM3 Reference time interval signal...

Page 337: ...us Priority controller Vector table address generator Standby release signal Interrupt request Internal bus IE PR ISP MK IF Interrupt request Priority controller Vector table address generator Standby...

Page 338: ...upt request flag IE Interrupt enable flag ISP In service priority flag MK Interrupt mask flag PR Priority specification flag E Software interrupt Internal bus Vector table address generator Interrupt...

Page 339: ...of interrupt request flags interrupt mask flags and priority specification flags corresponding to interrupt request sources Table 16 2 Various Flags Corresponding to Interrupt Request Sources Interru...

Page 340: ...s 1 The TMIF4 flag is R W enabled only when the watchdog timer is used as an interval timer If the watchdog timer is used in watchdog timer mode 1 set the TMIF4 flag to 0 2 Always set bits 6 and 7 of...

Page 341: ...upt function Cautions 1 If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1 the MK0 value becomes undefined 2 Because port 0 has an alternate function as an external int...

Page 342: ...PR0 use a 16 bit memory manipulation instruction for setting RESET input sets these registers to FFH Figure 16 4 Format of Priority Specification Flag Register Cautions 1 When the watchdog timer is us...

Page 343: ...to TMC03 of the 16 bit timer mode control register TMC0 to 0 0 0 before setting the valid edge of TI0 When using the INTP0 TI0 P00 pin as an external interrupt input pin INTP0 the valid edge of INTP0...

Page 344: ...igure 16 6 Format of Sampling Clock Select Register Caution fX 2N 1 is the clock supplied to the CPU fX 26 and fX 27 are the clocks supplied to the peripheral hardware fX 2N 1 stops in the HALT mode R...

Page 345: ...tected a When input is less than the sampling cycle tSMP b When input is equal to or twice the sampling cycle tSMP c When input is twice or more than the sampling cycle tSMP tSMP Sampling clock INTP0...

Page 346: ...into the stack and the IE flag is reset to 0 If a maskable interrupt request is acknowledged the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP f...

Page 347: ...PC and branched A new non maskable interrupt request generated during execution of a non maskable interrupt servicing program is acknowledged after execution of the current non maskable interrupt ser...

Page 348: ...in WDT WDTM3 0 with non maskable interrupt request selected Interrupt request generation WDT interrupt servicing Interrupt control register unaccessed Interrupt service start Interrupt request held p...

Page 349: ...maskable interrupt servicing program execution Main routine NMI request 1 Execution of 1 instruction NMI request 2 Execution of NMI request 1 NMI request 2 held pending Servicing of pending NMI reques...

Page 350: ...clock cycles 33 clock cycles Note If an interrupt request is generated just before a divide instruction the wait time is maximized Remark 1 clock cycle 1 fCPU fCPU CPU clock If two or more maskable i...

Page 351: ...low priority is serviced Start IF 1 MK 0 PR 0 Any simultaneously generated PR 0 interrupt requests Any simultaneously generated high priority interrupt requests IE 1 ISP 1 Vectored interrupt servicin...

Page 352: ...ged the contents of the program status word PSW and program counter PC are saved in the stacks in that order the IE flag is reset to 0 and the contents of the vector tables 003EH and 003FH are loaded...

Page 353: ...generated during interrupt servicing it is not acknowledged for multiple interrupt servicing Interrupt requests that are not enabled because the interrupt disabled state is set or they have a lower pr...

Page 354: ...d due to priority control The interrupt request INTyy generated during interrupt INTxx servicing is not acknowledged because its interrupt priority is lower than that of INTxx and multiple interrupt s...

Page 355: ...in interrupt INTxx servicing an EI instruction is not issued interrupt request INTyy is not acknowledged and multiple interrupt servicing is not generated The INTyy request is held pending and acknowl...

Page 356: ...n The BRK instruction does not belong to the above group of instructions However the software interrupt that is started by execution of the BRK instruction clears the IE flag to 0 Therefore even if a...

Page 357: ...Figure 16 17 Figure 16 17 Basic Configuration of Test Function IF Test input flag MK Test mask flag 16 5 1 Test function control registers The test function is controlled by the following two register...

Page 358: ...ormat of Interrupt Mask Flag Register 0H 16 5 2 Test input signal acknowledgment operation The internal test input signal INTWT is generated when the watch timer overflows This signal sets the WTIF fl...

Page 359: ...memory contents with ultra low power consumption Because this mode can be released by an interrupt request it enables intermittent operations to be carried out However because a wait time is necessar...

Page 360: ...gister Caution The wait time after STOP mode release does not include the time from STOP mode release to clock oscillation start see a below regardless of whether the STOP mode is released by RESET in...

Page 361: ...ts output latch Status before HALT instruction execution is held 16 bit timer event counter Operation enabled Operation stopped 8 bit timer event counter Operation enabled when TI1 and TI2 are Watchdo...

Page 362: ...Wait time will be as follows When vectored interrupt servicing is carried out 8 to 9 clocks When vectored interrupt servicing is not carried out 2 to 3 clocks b Release by non maskable interrupt reque...

Page 363: ...le 17 2 Operation After HALT Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt servicing 0 1 0 1 Next address instr...

Page 364: ...r OSTS the operating mode is set The operating status in the STOP mode is described below Table 17 3 STOP Mode Operating Status STOP Mode With Subsystem Clock Without Subsystem Clock Setting Item Cloc...

Page 365: ...struction at the next address is executed Figure 17 4 STOP Mode Release by Interrupt Request Generation Remark The broken line indicates the case when the interrupt request which has released the stan...

Page 366: ...5 0 MHz Table 17 4 Operation After STOP Mode Release Release Source MK PR IE ISP Operation Maskable interrupt request 0 0 0 Next address instruction execution 0 0 1 Interrupt servicing 0 1 0 1 Next a...

Page 367: ...after reset release When a high level is input to the RESET pin the reset is released and program execution starts after the lapse of the oscillation stabilization time 217 fX The reset applied by wat...

Page 368: ...cillation stop Oscillation stabilization time wait Normal operation reset processing Hi Z Watchdog timer overflow Internal reset signal Port pin X1 Normal operation Reset period oscillation stop Oscil...

Page 369: ...ent counter Timer register TM0 00H Compare register CR00 Undefined Capture register CR01 Undefined Clock select register TCL0 00H Mode control register TMC0 00H Output control register TOC0 00H 8 bit...

Page 370: ...l register ADTC 00H Automatic data transmit receive address pointer ADTP 00H Automatic data transmit receive interval specification register ADTI 00H Interrupt timing specification register SINT 00H A...

Page 371: ...I1 On chip pull down resistors are not On chip pull down resistors can be P34 TI2 P35 PCL P36 BUZ P37 provided specified in 1 bit units by mask option P70 to P74 On chip pull up resistors are not On c...

Page 372: ...apacity of the PD78P0208 can be selected by using the internal memory size switching register IMS The same memory map as that of the mask ROM version with a different internal memory capacity is possi...

Page 373: ...0204A CFH C8H PD780205 CAH PD780205A CFH CAH PD780206 CCH PD780208 CFH PD78P0208 CFH Caution When using the PD780204 780205 780206 and 780208 do not set any value other than the above IMS Value After...

Page 374: ...value other than those listed in Table 19 3 to IXS Figure 19 2 Format of Internal Expansion RAM Size Switching Register Table 19 3 lists the IXS setting values for a memory map equivalent to the mask...

Page 375: ...ble 19 4 below according to the setting of the CE OE and PGM pins The PROM contents can be read by setting the read mode Table 19 4 PROM Programming Operating Modes Pin RESET VPP VDD CE OE PGM D0 to D...

Page 376: ...10 6 Byte write mode A byte write is executed by applying a 0 1 ms program pulse active low to the PGM pin while CE L and OE H After this program verification can be performed by setting OE to L If p...

Page 377: ...N Last address of program Start Address G VDD 6 5 V VPP 12 5 V X 0 Latch Address Address 1 Latch Address Address 1 Latch Address Address 1 Latch X X 1 0 1 ms program pulse Verify 4 bytes Address N VDD...

Page 378: ...78 User s Manual U11302EJ4V0UM Figure 19 4 Page Program Mode Timing A0 A1 A2 to A16 D0 to D7 VPP VDD VPP VDD VDD VDD 1 5 CE VIL VIH PGM VIL VIH OE VIL VIH Page data latch Page program Program verify D...

Page 379: ...de Flowchart G Start address N Last address of program Start Address G Address Address 1 VDD 6 5 V VPP 12 5 V X 0 X X 1 0 1 ms program pulse Verify Address N VDD 4 5 to 5 5 V VPP VDD All bytes verifie...

Page 380: ...before VPP and removed after VPP 2 Ensure that VPP does not exceed 13 5 V including overshoot 3 Disconnecting the device while 12 5 V is being applied to VPP may have an adverse affect on reliability...

Page 381: ...to the VPP pin Unused pins are handled as shown in 1 5 Pin Configuration Top View 2 PROM programming mode 2 Supply 5 V to the VDD and VPP pins 3 Input the address of the data to be read to pins A0 to...

Page 382: ...ully tested by NEC Electronics before shipment due to the nature of PROM After the necessary data has been written it is recommended to implement a screening process that is the written contents shoul...

Page 383: ...TER 20 INSTRUCTION SET This chapter describes the instruction set for the PD780208 Subseries For details of the operations and mnemonics instruction codes of each instruction refer to the 78K 0 Series...

Page 384: ...rp either function names X A C etc or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 20 1 Operand Identifiers and Description Methods Identifier...

Page 385: ...C Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag NMIS Non maskable interrupt servicing flag Memory contents indicated by address or register contents i...

Page 386: ...HL A A HL byte 2 8 9 A HL byte HL byte A 2 8 9 HL byte A A HL B 1 6 7 A HL B HL B A 1 6 7 HL B A A HL C 1 6 7 A HL C HL C A 1 6 7 HL C A XCH A r Note 3 1 2 A r A saddr 2 4 6 A saddr A sfr 2 6 A sfr A...

Page 387: ...5 A CY A HL A HL byte 2 8 9 A CY A HL byte A HL B 2 8 9 A CY A HL B A HL C 2 8 9 A CY A HL C ADDC A byte 2 4 A CY A byte CY saddr byte 3 6 8 saddr CY saddr byte CY A r Note 4 2 4 A CY A r CY r A 2 4...

Page 388: ...addr16 3 8 9 A CY A addr16 CY A HL 1 4 5 A CY A HL CY A HL byte 2 8 9 A CY A HL byte CY A HL B 2 8 9 A CY A HL B CY A HL C 2 8 9 A CY A HL C CY AND A byte 2 4 A A byte saddr byte 3 6 8 saddr saddr byt...

Page 389: ...16 3 8 9 A A addr16 A HL 1 4 5 A A HL A HL byte 2 8 9 A A HL byte A HL B 2 8 9 A A HL B A HL C 2 8 9 A A HL C CMP A byte 2 4 A byte saddr byte 3 6 8 saddr byte A r Note 3 2 4 A r r A 2 4 r A A saddr 2...

Page 390: ...0 A3 0 HL 7 4 HL 3 0 Decimal Adjust Accumulator after Addition Decimal Adjust Accumulator after Subtract CY saddr bit 3 6 7 CY saddr bit CY sfr bit 3 7 CY sfr bit CY A bit 2 4 CY A bit CY PSW bit 3 7...

Page 391: ...bit 2 4 CY CY A bit CY PSW bit 3 7 CY CY PSW bit CY HL bit 2 6 7 CY CY HL bit SET1 saddr bit 2 4 6 saddr bit 1 sfr bit 3 8 sfr bit 1 A bit 2 4 A bit 1 PSW bit 2 6 PSW bit 1 HL bit 2 6 8 HL bit 1 CLR1...

Page 392: ...P 1 rp 1 4 SP 1 rpH SP 2 rpL SP SP 2 POP PSW 1 2 PSW SP SP SP 1 R R R rp 1 4 rpH SP 1 rpL SP SP SP 2 MOVW SP word 4 10 SP word SP AX 2 8 SP AX AX SP 2 8 AX SP BR addr16 3 6 PC addr16 addr16 2 6 PC PC...

Page 393: ...PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr16 3 8 PC PC 3 jdisp8 if A bit 1 then reset A bit PSW bit addr16 4 12 PC PC 4 jdisp8 if PSW bit 1 then reset PSW bit HL bit addr16 3 10 12 PC...

Page 394: ...STRUCTION SET 394 User s Manual U11302EJ4V0UM 20 3 Instructions Listed by Addressing Type 1 8 bit instructions MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MULU DIVUW INC DEC ROR ROL RORC ROLC ROR4 ROL4 P...

Page 395: ...SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP r...

Page 396: ...VW SP MOVW MOVW Note Only when rp BC DE or HL 3 Bit manipulation instructions MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 BT BF BTCLR Second Operand A bit sfr bit saddr bit PSW bit HL bit CY addr16 None A bit M...

Page 397: ...ructions CALL CALLF CALLT BR BC BNC BZ BNZ BT BF BTCLR DBNZ Second Operand AX addr16 addr11 addr5 addr16 Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound instruction BT BF BTCLR DBNZ...

Page 398: ...em clock or Main system clock only Main system clock or subsystem clock selectable subsystem clock selectable I O ports 68 pins 72 pins 74 pins Total of VFD display output pins 34 pins 48 pins 53 pins...

Page 399: ...on of the development tools Support for PC98 NX series Unless otherwise specified products supported by IBM PC ATTM compatible machines can be used for PC98 NX series computers When using PC98 NX seri...

Page 400: ...ge C compiler package Device file C library source fileNote 1 Debugging software Integrated debugger System simulator Host machine PC or EWS Interface adapter PC card interface etc In circuit emulator...

Page 401: ...with a device file DF780208 sold separately Caution when using RA78K0 in PC environment This assembler package is a DOS based application It can also be used in Windows however by using the Project Ma...

Page 402: ...K0 L Host Machine OS Supply Medium AB13 PC 9800 series Windows Japanese version 3 5 inch 2HD FD BB13 IBM PC AT and compatibles Windows English version 3P16 HP9000 series 700 HP UX Rel 10 10 DAT 3K13 S...

Page 403: ...s to control the PG 1500 from a host machine which is connected to the PG 1500 via serial parallel interface cable s Part Number S PG1500 Remark in the part number differs depending on the host machin...

Page 404: ...This board is used for extending the IE 78K0 NS functions With the addition of this board the addition of a coverage function enhancement of tracer and timer functions and other such debugging functi...

Page 405: ...th an integrated debugger ID78K0 This emulator is used with an emulation probe and interface adapter for connecting a host machine This adapter is necessary when a PC 9800 series PC except notebook ty...

Page 406: ...in circuit emulators for the 78K 0 Series The Integrated debugger ID78K0 NS is Windows based software supporting in circuit emulators It has improved C compatible debugging functions and can display...

Page 407: ...prompt when using in Windows Part Number S RX78013 Caution When purchasing the RX78K0 fill in the purchase application form in advance and sign the user agreement Remark and in the part number differ...

Page 408: ...that in circuit emulator can operate as an equivalent to the IE 78001 R A by replacing its internal break board with the IE 78001 R BK Table B 1 Method for Upgrading from Former In Circuit Emulator f...

Page 409: ...D E F G H I J K L M N O P Q R S 24 6 21 15 18 6 4 C 2 0 8 12 0 22 6 25 3 6 0 16 6 19 3 8 2 8 0 2 5 2 0 0 35 2 3 1 5 0 969 0 827 0 591 0 732 4 C 0 079 0 031 0 472 0 89 0 996 0 236 0 654 076 0 323 0 315...

Page 410: ...05 0 65 0 02 19 12 35 0 05 0 001 0 002 0 002 _0 002 0 001 0 002 0 003 _0 002 0 003 _0 002 0 003 _0 002 0 001 _0 001 0 001 _0 002 0 001 _0 002 G 1 142 0 742 0 748 0 486 Figure B 3 Recommended Footprin...

Page 411: ...ensei Machida Mfg Co Ltd and the TGF 100RBP is a product of TOKYO ELETECH CORPORATION Table B 2 Distance Between IE System and Conversion Adapter Emulation Probe Conversion Adapter Distance Between IE...

Page 412: ...nnection Conditions of Target System When NP H100GF TQ Is Used Emulation probe NP H100GF TQ Emulation board IE 780208 NS EM1 42 mm 45 mm Target system 11 mm Conversion adapter TGF 100RBP 27 5 mm Pin 1...

Page 413: ...compare register CR10 CR20 153 8 bit timer mode control register TMC1 155 8 bit timer output control register TOC1 156 8 bit timer register 1 TM1 153 8 bit timer register 2 TM2 153 External interrupt...

Page 414: ...t register SCS 134 344 Serial bus interface control register SBIC 214 220 233 251 Serial I O shift register 0 SIO0 209 Serial I O shift register 1 SIO1 259 Serial operating mode register 0 CSIM0 211 2...

Page 415: ...CSIM0 Serial operating mode register 0 211 218 232 250 CSIM1 Serial operating mode register 1 262 269 273 D DSPM0 Display mode register 0 104 303 DSPM1 Display mode register 1 107 303 DSPM2 Display m...

Page 416: ...33 251 SCS Sampling clock select register 134 344 SINT Interrupt timing specification register 216 235 252 SIO0 Serial I O shift register 0 209 SIO1 Serial I O shift register 1 259 SVA Slave address r...

Page 417: ...er CHAPTER 9 Format WATCHDOG TIMER Deletion of CHAPTER 10 6 BIT UP DOWN COUNTER CHAPTER 10 6 BIT UP DOWN COUNTER Addition of Caution when using standby function on Figure 12 2 A D CHAPTER 12 Converter...

Page 418: ...of Caution in 4 2 10 Port 12 Addition of Note in Figure 5 3 Format of Processor Clock Control Register CHAPTER 5 CLOCK GENERATOR Modification of Caution in Figure 6 8 Format of External Interrupt Mode...

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