CHAPTER 5 CLOCK GENERATOR
101
User’s Manual U11302EJ4V0UM
Figure 5-1. Clock Generator Block Diagram
Notes 1.
Bit 6 of display mode register 0 (DSPM0)
2.
Bits 4 to 7 of display mode register 1 (DSPM1)
Subsystem
clock oscillator
f
XT
XT2
XT1/P04
FRC
Selector
Clock output function
Main system
clock oscillator
X2
X1
f
X
STOP
MCC
FRC
CLS
CSS
PCC2 PCC1 PCC0
Processor clock control register
Internal bus
Standby
controller
CPU clock
(f
CPU
)
2
f
X
2
2
f
X
2
3
f
X
2
4
f
X
Prescaler
Clock to
peripheral
hardware
3
To INTP0
sampling
clock
Prescaler
Noise
eliminator
DIGS0 to
DIGS3
Note 2
DSPM06
Note 1
f
X
/8
f
X
/16
Watch timer
Selector
Watchdog timer
f
X
Selector
1/2
2
f
XT
