NEC mPD780208 Subseries, User Manual

Page: 183 / 418

CHAPTER 10 CLOCK OUTPUT CONTROLLER
183
User’s Manual U11302EJ4V0UM
10.2 Clock Output Controller Configuration
The clock output controller consists of the following hardware.
Table 10-1. Clock Output Controller Configuration
Item Configuration
Control registers Timer clock select register 0 (TCL0)
Port mode register 3 (PM3)
Figure 10-2. Clock Output Controller Block Diagram
10.3 Clock Output Function Control Registers
The following two registers are used to control the clock output function.
• Timer clock select register 0 (TCL0)
• Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets the PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TCL0 to 00H.
Remark Besides setting the PCL output clock, TCL0 sets the 16-bit timer register count clock.
f
X
/2
3
f
X
/2
4
f
X
/2
5
f
X
/2
6
f
X
/2
7
f
X
/2
8
f
XT
Selector
Synchronizing
circuit
P35
output
latch
4
PCL/P35
PM35 CLOE TCL03 TCL02 TCL01 TCL00
Internal bus
Timer clock select register 0
Port mode register 3