CHAPTER 15 VFD CONTROLLER/DRIVER
307
User’s Manual U11302EJ4V0UM
Figure 15-4. Format of Display Mode Register 1
DIMS0
Display mode cycle setting
0
1024/f
X
is 1 display cycle. (1 display cycle = 204.8
µ
s: when operated at 5.0 MHz)
1
2048/f
X
is 1 display cycle. (1 display cycle = 409.6
µ
s: when operated at 5.0 MHz)
DIMS3 DIMS2 DIMS1
VFD output signal cut width
0
0
0
1/16
0
0
1
2/16
0
1
0
4/16
0
1
1
6/16
1
0
0
8/16
1
0
1
10/16
1
1
0
12/16
1
1
1
14/16
DIGS3 DIGS2 DIGS1 DIGS0
Display digit (display mode 1) DSPM05 = 0
Display pattern (display mode 2) DSPM05 = 1
0
0
0
0
Display stopped (static display)
Note
Display stopped (static display)
Note
0
0
0
1
2 digits
2 patterns
0
0
1
0
3 digits
3 patterns
0
0
1
1
4 digits
4 patterns
0
1
0
0
5 digits
5 patterns
0
1
0
1
6 digits
6 patterns
0
1
1
0
7 digits
7 patterns
0
1
1
1
8 digits
8 patterns
1
0
0
0
9 digits
9 patterns
1
0
0
1
10 digits
10 patterns
1
0
1
0
11 digits
11 patterns
1
0
1
1
12 digits
12 patterns
1
1
0
0
13 digits
13 patterns
1
1
0
1
14 digits
14 patterns
1
1
1
0
15 digits
15 patterns
1
1
1
1
16 digits
16 patterns
Note
Static display is possible when display stop is selected, by manipulating the port output latch.
Remark
f
X
:
Main system clock oscillation frequency
DSPM05: Bit 5 of display mode register 0 (DSPM0)
7
1
0
6
5
4
3
2
DIGS3
DIMS1 DIMS0
DIGS2 DIGS1 DIGS0 DIMS3 DIMS2
Symbol
DSPM1
F F A 1 H
0 0 H
R/W
Address
After reset
R/W
