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National Semiconductor CP3BT26, User Manual

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CP3BT26

Direct mode supports two bus policies: intermittent and con-
tinuous. In intermittent mode, the DMAC gives bus master-
ship back to the CPU after every cycle. In continuous mode,
the DMAC remains bus master until the transfer is complet-
ed. The maximum bus throughput in intermittent mode is
one transfer for every three System Clock cycles. The max-
imum bus throughput in continuous mode is one transfer for
every clock cycle.

The I/O device which made the DMA request is called the
implied I/O device. The other device can be either memory
or another I/O device, and is called the addressed device. 

Because only one address is required in direct mode, this
address is taken from the corresponding ADCAn counter.
The DMAC channel generates either a read or a write bus
cycle, as controlled by the DMACNTLn.DIR bit.

When the DMACNTLn.DIR bit is clear, a read bus cycle
from the addressed device is performed, and the data is
written to the implied I/O device. When the DMACNTLn.DIR
bit is set, a write bus cycle to the addressed device is per-
formed, and the data is read from the implied I/O device.

The configuration of either address freeze or address up-
date (increment or decrement) is independent of the num-
ber of transferred bytes, transfer direction, or number of
bytes in each DMAC transfer cycle. All these can be config-
ured for each channel by programming the appropriate con-
trol register. 

Whether 8 or 16 bits are transferred in each cycle is select-
ed by the DMACNTLn.TCS register bit. After the data item
has been transferred, the BLTCn counter is decremented by
one. The ADCAn counter is updated according to the INCA
and ADA fields in the DMACNTLn register.

9.2.2

Indirect (Memory-To-Memory) Transfers

In indirect (memory-to-memory) mode, data transfers use
two consecutive bus cycles. The data is first read into a tem-
porary register, and then written to the destination in the fol-
lowing cycle. This mode is slower than the direct (flyby)
mode, but it provides support for different source and desti-
nation bus widths. Indirect mode must be used for transfers
between memory devices.

If an intermittent bus policy is used, the maximum through-
put is one transfer for every five clock cycles. If a continuous
bus policy is used, maximum throughput is one transfer for
every two clock cycles.

When the DMACNTLn.DIR bit is 0, the first bus cycle reads
data from the source using the ADCAn counter, while the
second bus cycle writes the data into the destination using
the ADCBn counter. When the DMACNTLn.DIR bit is set,
the first bus cycle reads data from the source using the AD-
CBn counter, while the second bus cycle writes the data into
the destination addressed by the ADCAn counter. 

The number of bytes transferred in each cycle is taken from
the DMACNTLn.TCS register bit. After the data item has
been transferred, the BLTCn counter is decremented by
one. The ADCAn and ADCBn counters are updated accord-
ing to the INCA, INCB, ADA, and ADB fields in the
DMACNTLn register.

9.3

OPERATION MODES

The DMAC operates in three different block transfer modes:
single transfer, double buffer, and auto-initialize.

9.3.1

Single Transfer Operation

This mode provides the simplest way to accomplish a single
block data transfer.

Initialization

1. Write the block transfer addresses and byte count into

the corresponding ADCAn, ADCBn, and BLTCn
counters.

2. Clear the DMACNTLn.OT bit to select non-auto-initial-

ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.

3. Set the DMACNTLn.CHEN bit to activate the channel

and enable it to respond to DMA transfer requests.

Termination

When the BLTCn counter reaches 0:

1. The transfer operation terminates.
2. The DMASTAT.TC and DMASTAT.OVR bits are set, and

the DMASTAT.CHAC bit is cleared.

3. An interrupt is generated if enabled by the

DMACNTLn.ETC or DMACNTLn.EOVR bits.

The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.

9.3.2

Double Buffer Operation

This mode allows software to set up the next block transfer
while the current block transfer proceeds.

Initialization

1. Write the block transfer addresses and byte count into

the ADCAn, ADCBn, and BLTCn counters.

2. Clear the DMACNTLn.OT bit to select non-auto-initial-

ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.

3. Set the DMACNTLn.CHEN bit. This activates the chan-

nel and enables it to respond to DMA transfer requests.

4. While the current block transfer proceeds, write the ad-

dresses and byte count for the next block into the
ADRAn, ADRBn, and BLTRn registers. The BLTRn reg-
ister must be written last, because it sets the DMAS-
TAT.VLD bit which indicates that all the parameters for
the next transfer have been updated.

Continuation/Termination

When the BLTCn counter reaches 0:

1. The DMASTAT.TC bit is set.
2. An interrupt is generated if enabled by the

DMACNTLn.ETC bit.

3. The DMAC channel checks the value of the VLD bit.

If the DMASTAT.VLD bit is set:

1. The channel copies the ADRAn, ADRBn, and BLTRn

values into the ADCAn, ADCBn, and BLTCn registers.

2. The DMASTAT.VLD bit is cleared.
3. The next block transfer is started.

Summary of Contents for CP3BT26

Page 1: ...ion of embedded Bluetooth products the CP3BT26 is backed up by the software resources designers need for rapid time to market including an operating system Blue tooth protocol stack implementation peripheral drivers ref erence designs and an integrated development environment Combined with a Bluetooth radio transceiver such as National s LMX5252 the CP3BT26 provides a com plete Bluetooth system so...

Page 2: ... Functional Description 79 16 2 Touchscreen Interface 81 16 3 ADC Operation in Power Saving Modes 83 16 4 Freeze 83 16 5 ADC Register Set 83 17 0 Random Number Generator RNG 88 17 1 Freeze 88 17 2 Random Number Generator Register Set 89 18 0 USB Controller 90 18 1 Functional States 90 18 2 Endpoint Operation 91 18 3 USB Controller Registers 93 18 4 Transceiver Interface 108 19 0 CAN Module 109 19 ...

Page 3: ...peripheral I O Programmable I O pin characteristics TRI STATE out put push pull output weak pull up input high imped ance input Schmitt triggers on general purpose inputs Multi Input Wake Up MIWU capability Power Supply I O port operation at 2 5V to 3 3V Core logic operation at 2 5V On chip power on reset Temperature Range 40 C to 85 C Industrial Packages LQFP 128 LQFP 144 Complete Development Env...

Page 4: ... I O pins or ganized into seven ports called Port B Port C Port E Port G Port H Port I and Port J Each pin can be configured to operate as a general purpose input or general purpose out put In addition many I O pins can be configured to operate as inputs or outputs for on chip peripheral modules such as the UART timers or Microwire SPI interface The I O pin characteristics are fully programmable E...

Page 5: ...ol One UART channel supports hardware flow control DMA and USART capability syn chronous mode The UARTs offer a wake up condition from the low power modes using the Multi Input Wake Up module 3 11 ADVANCED AUDIO INTERFACE The audio interface provides a serial synchronous full du plex interface to CODECs and similar serial devices Trans mit and receive paths operate asynchronously with respect to e...

Page 6: ...he Timing and Watchdog Module TWM contains a Real Time timer and a Watchdog unit The Real Time Clock Tim ing function can be used to generate periodic real time based system interrupts The timer output is one of 16 in puts to the Multi Input Wake Up module which can be used to exit from a power saving mode The Watchdog unit is de signed to detect the application program getting stuck in an infinit...

Page 7: ...ic rate In the network mode the inter face transfers multiple words at a periodic rate The periodic rate is also called a data frame and each word within one frame is called a slot The beginning of each new data frame is marked by the frame sync signal 3 23 SERIAL DEBUG INTERFACE The Serial Debug Interface module SDI module provides a JTAG based serial link to an external debugger for exam ple run...

Page 8: ...GND D D SDA ACCESS bus SCL PH0 RXD1 WUI11 PH1 TXD1 WUI12 UART1 MIWU PH2 RXD1 WUI13 PH3 TXD1 WUI14 UART2 MIWU PH4 RXD1 WUI15 PH5 TXD1 WUI16 UART3 MIWU MIWU PG6 BTSEQ2 WUI10 PJ0 WUI18 PJ1 WUI19 PJ2 WUI20 PJ3 WUI21 PJ4 WUI22 PJ5 WUI23 PJ6 WUI24 8 8 PB 7 0 PC 7 0 GPIO AVCC AGND 1 1 X1CKI BBCLK 12 MHz Crystal or Ext Clock External Bus Interface X1CKO X2CKI 32 768 kHz Crystal RF Interface X2CKO ADVCC GN...

Page 9: ...h internal weak pull up None None TDI 1 Input JTAG Test Data Input with internal weak pull up None None TDO 1 Output JTAG Test Data Output None None RDY 1 Output NEXUS Ready Output None None VCC 6 Input 2 5V Core Logic Power Supply None None GND 6 Input Core Ground None None IOVCC 15 Input 2 5 3 3V I O Power Supply None None IOGND 14 Input I O Ground None None AVCC 1 Input PLL Analog Power Supply ...

Page 10: ...AAI Receive Frame Sync NMI Non Maskable Interrupt Input PF0 1 I O Generic I O MSK SPI Shift Clock TIO1 Versatile Timer Channel 1 PF1 1 I O Generic I O MDIDO SPI Master In Slave Out TIO2 Versatile Timer Channel 2 PF2 1 I O Generic I O MDODI SPI Master Out Slave In TIO3 Versatile Timer Channel 3 PF3 1 I O Generic I O MWCS SPI Slave Select Input TIO4 Versatile Timer Channel 4 PF4 1 I O Generic I O SC...

Page 11: ...nel 14 PH4 1 I O Generic I O RXD3 UART Channel 3 Receive Data Input WUI15 Multi Input Wake Up Channel 15 PH5 1 I O Generic I O TXD3 UART Channel 3 Transmit Data Output WUI16 Multi Input Wake Up Channel 16 PH6 1 I O Generic I O CANRX CAN Receive Input WUI17 Multi Input Wake Up Channel 17 PH7 1 I O Generic I O CANTX CAN Transmit Output PJ0 1 I O Generic I O WUI18 Multi Input Wake Up Channel 18 PJ1 1...

Page 12: ...h internal weak pull up None None TDI 1 Input JTAG Test Data Input with internal weak pull up None None TDO 1 Output JTAG Test Data Output None None RDY 1 Output NEXUS Ready Output None None VCC 6 Input 2 5V Core Logic Power Supply None None GND 6 Input Core Ground None None IOVCC 10 Input 2 5 3 3V I O Power Supply None None IOGND 11 Input I O Ground None None AVCC 1 Input PLL Analog Power Supply ...

Page 13: ...one WR1 1 Output External Memory Write High Byte None None RD 1 Output External Memory Read None None PE0 1 I O Generic I O RXD0 UART0 Receive Data Input PE1 1 I O Generic I O TXD0 UART0 Transmit Data Output PE2 1 I O Generic I O RTS UART0 Ready To Send Output PE3 1 I O Generic I O CTS UART0 Clear To Send Input PE4 1 I O Generic I O CKX UART0 Clock Input TB Multi Function Timer Port B PE5 1 I O Ge...

Page 14: ... 1 I O Generic I O RXD1 UART Channel 1 Receive Data Input WUI11 Multi Input Wake Up Channel 11 PH1 1 I O Generic I O TXD1 UART Channel 1 Transmit Data Output WUI12 Multi Input Wake Up Channel 12 PH2 1 I O Generic I O RXD2 UART Channel 2 Receive Data Input WUI13 Multi Input Wake Up Channel 13 PH3 1 I O Generic I O TXD2 UART Channel 2 Transmit Data Output WUI14 Multi Input Wake Up Channel 14 PH4 1 I...

Page 15: ...RA register holds a subroutine return ad dress The R12 and R13 registers are available to hold base addresses used in the index addressing mode If a general purpose register is specified by an operation that is 8 bits long only the lower byte of the register is used the upper part is not referenced or modified Similarly for word operations on register pairs only the lower word is used The upper wo...

Page 16: ...equal N The Negative bit indicates the result of the last comparison operation with the operands in terpreted as signed integers 0 Second operand greater than or equal to first operand 1 Second operand less than first operand E The Local Maskable Interrupt Enable bit en ables or disables maskable interrupts If this bit and the Global Maskable Interrupt Enable I bit are both set all interrupts are ...

Page 17: ...IDT is held in the INTBASE register which is not affected by the state of the ED bit 0 Interrupt dispatch table has 16 bit entries 1 Interrupt dispatch table has 32 bit entries SR The Short Register bit enables a compatibility mode for the CR16B large model In the CR16C core registers R12 R13 and RA are extended to 32 bits In the CR16B large mod el only the lower 16 bits of these registers are use...

Page 18: ...he operand is ad dressed using a relative value displace ment encoded in the instruction This displacement is relative to the current Program Counter PC a general pur pose register or a register pair In branch instructions the displacement is always relative to the current value of the PC Register For example the follow ing instruction causes an unconditional branch to an address 10 ahead of the c...

Page 19: ...am stack pointer User mode can only be entered using the JUSR instruction which performs a jump and sets the PSR U bit User mode is exited when an exception is taken and re entered when the exception handler returns In user mode the LPRD in struction cannot be used to change the state of processor registers such as the PSR 5 7 INSTRUCTION SET Table 4 lists the operand specifiers for the instructio...

Page 20: ...st 16 Rdest 16 Rsrc 16 imm MULSB Rsrc Rdest Multiply Rdest 16 Rdest 8 Rsrc 8 MULSW Rsrc RPdest Multiply RPdest RPdest 16 Rsrc 16 MULUW Rsrc RPdest Multiply RPdest RPdest 16 Rsrc 16 SUBi Rsrc imm Rdest Subtract Rdest Rdest Rsrc imm SUBD RPsrc imm RPdest Subtract RPdest RPdest RPsrc imm SUBCi Rsrc imm Rdest Subtract with carry Rdest Rdest Rsrc imm CMPi Rsrc imm Rdest Compare Rdest Rsrc imm CMPD RPsr...

Page 21: ... Iposition Rindex abs TBIT TBITi Rposition imm Rsrc Test a bit in a register Test a bit in memory Iposition disp Rbase Iposition disp RPbase Iposition Rindex disp RPbasex Iposition abs Iposition Rindex abs LPR Rsrc Rproc Load processor register LPRD RPsrc Rprocd Load double processor register SPR Rproc Rdest Store processor register SPRD Rprocd RPdest Store 32 bit processor register Bcond disp9 Co...

Page 22: ...RPbase Rdest Load register pair relative STORi Rsrc disp Rbase Store register relative Rsrc disp RPbase Store register pair relative Rsrc abs Store absolute Rsrc Rindex disp RPbasex Store register pair relative index Rsrc Rindex abs Store absolute index STORD RPsrc disp Rbase Store register relative RPsrc disp RPbase Store register pair relative RPsrc abs Store absolute RPsrc Rindex disp RPbasex S...

Page 23: ...s R2 R5 R8 R11 to memory starting at R7 R6 DI Disable maskable interrupts EI Enable maskable interrupts EIWAIT Enable maskable interrupts and wait for interrupt NOP No operation WAIT Wait for interrupt Table 5 Instruction Set Summary Mnemonic Operands Description ...

Page 24: ...ode is selected without re gard to the states of the EMPTY bits See Section 8 4 2 for more details In the DEV environment the on chip flash memory is dis abled and the corresponding region of the address space is mapped to external memory DEVINT mode is equivalent to DEV mode but maps static memory zone 0 to the on chip memory Start Address End Address Size in Bytes Description BIU Zone 00 0000h 0...

Page 25: ... of a bus cycle This holds the data on the data bus for an extended number of clock cy cles 6 4 BIU CONTROL REGISTERS The BIU has a set of control registers that determine how many wait cycles and hold cycles are to be used for access ing memory During initialization of the system these regis ters should be programmed with appropriate values so that the minimum allowable number of cycles is used T...

Page 26: ...s the number of TIW internal wait state clock cycles added for each memory access ranging from 000b for no additional TIW wait cycles to 111b for seven additional TIW wait cycles These bits are ignored if the SZCFG0 FRE bit is set HOLD The Memory Hold field specifies the number of Thold clock cycles used for each memory access ranging from 00b for no Thold cycles to 11b for three Thold clock cycle...

Page 27: ...al read operation takes at least two clock cycles 0 Normal read cycles 1 Fast read cycles IPST The Post Idle bit controls whether an idle cycle follows the current bus cycle when the next bus cycle accesses a different zone 0 No idle cycle 1 Idle cycle inserted IPRE The Preliminary Idle bit controls whether an idle cycle is inserted prior to the current bus cycle when the new bus cycle accesses a ...

Page 28: ...single cycle access This limits the maximum CPU operat ing frequency to 24 MHz For a read operation in normal read mode SZCFG0 FRE 0 the number of inserted wait cycles is specified in the SZCFG0 WAIT field The total number of wait cycles is the value in the WAIT field plus 1 so it can range from 1 to 8 The number of inserted hold cycles is specified in the SCCFG0 HOLD field which can range from 0 ...

Page 29: ...ENV1 CPUCLK pin is high impedance 1 Main Clock is driven on the ENV1 CPU CLK pin SCLKOE The SCLKOE bit controls whether the Slow Clock is driven on the ENV2 SLOWCLK pin 0 ENV2 SLOWCLK pin is high impedance 1 Slow Clock is driven on the ENV2 SLOW CLK pin USB_ENABLE The USB_ENABLE bit can be used to force an external USB transceiver into its low power mode The power mode is dependent on the USB cont...

Page 30: ...ccurred since this bit was last cleared 1 A software ISP reset has occurred since this bit was last cleared 7 3 SOFTWARE RESET REGISTER SWRESET The SWRESET register is a byte wide write only register which provides a mechanism for software to initiate a reset into ISP mode without regard to the status of the EMPTY bits in the flash protection word This form of reset is only al lowed when all of th...

Page 31: ...should clear all write enable bits to protect the flash program memory against any unintended writes 8 1 2 Global Protection The WRPROT field in the Protection Word controls global write protection The Protection Word is located in a special flash memory outside of the CPU address space If a major ity of the bits in the 3 bit WRPROT field are clear write pro tection is enabled Enabling this mode p...

Page 32: ...nformation Block 2 The CPU can write Information Block 2 only when global write protection is disabled Erasing Information Block 2 also erases Main Block 2 8 3 FLASH MEMORY OPERATIONS Flash memory programming erasing and writing can be performed on the flash data memory while the CPU is exe cuting out of flash program memory Although the CPU can execute out of flash data memory it cannot erase or ...

Page 33: ...comes clear again 6 Check the Erase Error EERR bit in the FMSTAT or FSMSTAT register to confirm successful erase of the block 7 Clear the MER bit 8 3 6 Main Block Write Writing is only allowed when global write protection is dis abled Writing by the CPU is only allowed when the write en able bit is set for the sector which contains the word to be written The CPU cannot write the Boot Area Only wor...

Page 34: ...ea encod ings EMPTY The EMPTY field indicates whether the flash program memory has been programmed or should be treated as blank If a majority of the three EMPTY bits are clear the flash program memory is treated as programmed If a major ity of the EMPTY bits are set the flash pro gram memory is treated as empty If the ENV 1 0 inputs see Section 6 1 are sam pled high at reset and the EMPTY bits in...

Page 35: ...Device starts in IRE ERE mode from address 0 Empty ISP Defined Device starts in ISP mode from Code Area start address Empty ISP Not Defined Device starts in ISP mode and is kept in its reset state Empty No ISP Don t Care Table 16 Flash Memory Interface Registers Program Memory Data Memory Description FMIBAR FF F940h FSMIBAR FF F740h Flash Memory Information Block Address Register FMIBDR FF F942h F...

Page 36: ...3 Flash Memory 0 Write Enable Register FM0WER FSM0WER The FM0WER register controls section level write protec tion for the first half of the flash program memory The FMS0WER registers controls section level write protection for the flash data memory Each data block is divided into 16 8K byte sections Each bit in the FM0WER and FSM0WER registers controls write protection for one of these sections T...

Page 37: ...is clear after reset The flash program and data mem ories share a single interrupt channel but have independent interrupt enable control bits 0 No interrupt request is asserted to the ICU when the FMFULL bit is cleared 1 An interrupt request is made when the FMFULL bit is cleared and new data can be written into the write buffer PE The Program Enable bit controls write access of the CPU to the fla...

Page 38: ...ates whether the write buffer for programming is full or not When the buffer is full new erase and write requests may not be made The IENPROG bit can be enabled to trigger an in terrupt when the buffer is ready to receive a new request 0 Buffer is ready to receive new erase or write requests 1 Buffer is full No new erase or write re quests can be accepted DERR The Data Loss Error bit indicates tha...

Page 39: ...page erase pulse width of 4096 FTPER 1 prescaler output clocks 8 5 13 Flash Memory Module Erase Time Reload Register 0 FMMERASE0 FSMMERASE0 The FMMERASE0 FSMMERASE0 register is a byte wide read write register that controls the module erase pulse width Software must not modify this register while a pro gram erase operation is in progress FMBUSY set At re set this register is initialized to EAh if t...

Page 40: ... mode dependent on USB controller status and programming of the Function Word 8 5 18 Flash Memory Auto Read Register 1 FMAR1 FSMAR1 The FMAR1 register contains a copy of the Protection Word from Information Block 1 The Protection Word is sampled at reset The contents of the FMAR1 register define the cur rent Flash memory protection settings The CPU bus mas ter has read only access to this register...

Page 41: ...endent of the num ber of transferred bytes transfer direction or number of bytes in each DMAC transfer cycle All these can be config ured for each channel by programming the appropriate con trol registers Each DMAC channel has eight control registers DMAC channels are described hereafter with the suffix n where n 0 to 3 representing the channel number in the register names 9 1 CHANNEL ASSIGNMENT T...

Page 42: ...the data into the destination using the ADCBn counter When the DMACNTLn DIR bit is set the first bus cycle reads data from the source using the AD CBn counter while the second bus cycle writes the data into the destination addressed by the ADCAn counter The number of bytes transferred in each cycle is taken from the DMACNTLn TCS register bit After the data item has been transferred the BLTCn count...

Page 43: ... software DMA transfer request must be used for block copy ing between memory devices When the DMACNTLn SWRQ bit is set the corresponding DMA channel receives a DMA transfer request When the DMACNTLn SWRQ bit is clear the software DMA transfer request of the corresponding channel is inactive For each channel use the software DMA transfer request only when the corresponding hardware DMA request is ...

Page 44: ...B Address register is a 32 bit read write regis ter It holds the 24 bit starting address of either the next source data block or the next destination data area accord ing to the DIR bit in the CNTLn register In direct flyby mode this register is not used The upper 8 bits of the AD CRBn register are reserved and always clear 9 6 5 Block Length Counter Register BLTCn The Block Length Counter registe...

Page 45: ...is initialized OT The Operation Type bit specifies the operation mode of the DMA controller 0 Single buffer mode or double buffer mode enabled 1 Auto Initialize mode enabled BPC The Bus Policy Control bit specifies the bus policy applied by the DMA controller The op eration mode can be either intermittent cycle stealing or continuous burst 0 Intermittent operation The DMAC chan nel relinquishes th...

Page 46: ...but the parameters for the next transfer address and block length are not valid DMASTAT VLD 0 In auto initialize mode DMACNTLn OT 1 The OVR bit is set when the present transfer is completed BLTCn 0 and the DMAS TAT TC bit is still set In single buffer mode Operates in the same way as double buffer mode In single buffered mode the DMAS TAT VLD bit should always be clear so it will also be set when ...

Page 47: ...abled by the E bit in the PSR register The EI and DI instructions are used to set enable and clear disable this bit The glo bal maskable interrupt enable bit I bit in the PSR must also be set before any maskable interrupts are taken Each interrupt source can be individually enabled or dis abled under software control through the ICU interrupt en able registers and also through interrupt enable bit...

Page 48: ...edge of the NMI pin TST EN and ENLCK are cleared on reset When writing to this register all reserved bits must be written with 0 for the device to function properly EN The EXNMI trap enable bit is one of two bits that can be used to enable NMI interrupts The bit is cleared by hardware at reset and whenever the NMI interrupt occurs EXN MI EXT set It is intended for applications where the NMI input ...

Page 49: ...ple IENA47 controls IRQ47 0 Interrupt is disabled 1 Interrupt is enabled 10 3 7 Interrupt Status Register 0 ISTAT0 The ISTAT0 register is a word wide read only register It in dicates which maskable interrupt inputs to the ICU are ac tive These bits are not affected by the state of the corresponding IENA bits IST The Interrupt Status bits indicate if a maskable interrupt source is signalling an in ...

Page 50: ...mit ed only by the available memory for the interrupt stack IRQ Number Description IRQ47 TWM Timer 0 IRQ46 Bluetooth LLC 0 IRQ45 Bluetooth LLC 1 IRQ44 Bluetooth LLC 2 IRQ43 Bluetooth LLC 3 IRQ42 Bluetooth LLC 4 IRQ41 Bluetooth LLC 5 IRQ40 USB Interface IRQ39 DMA Channel 0 IRQ38 DMA Channel 1 IRQ37 DMA Channel 2 IRQ36 DMA Channel 3 IRQ35 CAN IRQ34 Advanced Audio Interface AAI IRQ33 UART0 RX IRQ32 C...

Page 51: ...d Reset Module Reset Module Device Reset Stretched Reset Stop Main Osc Good Main Clock Power On Reset Module POR Start Up Delay 14 Bit Timer TWM Invalid Watchdog Service Flash Interface Program Erase Busy External Reset Good Slow Clock Start Up Delay 8 Bit Timer Auxiliary Clock 1 4 Bit Aux1 Prescaler Auxiliary Clock 2 4 Bit Aux2 Prescaler Slow Clock Slow Clock Select Main Clock 8 Bit Prescaler Mux...

Page 52: ...aced close to the X1CKI X1CKO and X2CKI X2CKO de vice input pins to keep the printed trace lengths to an abso lute minimum Figure 5 shows the external crystal network for the X1CKI and X1CKO pins Figure 6 shows the external crystal net work for the X2CKI and X2CKO pins Table 21 shows the component specifications for the main crystal network and Table 22 shows the component specifications for the 3...

Page 53: ...that the Slow Clock is stable For systems that do not require a reduced power consump tion mode the external crystal network may be omitted for the Slow Clock In that case the Slow Clock can be synthe sized by dividing the Main Clock by a prescaler factor The prescaler circuit consists of a fixed divide by 2 counter and a programmable 8 bit prescaler register This allows a choice of clock divisors...

Page 54: ... essary to use an external reset circuit to insure proper de vice initialization Figure 7 shows an example of an external reset circuit Figure 7 External Reset Circuit The value of R should be less than 50K ohms The RC time constant of the circuit should be 5 times the power supply rise time The time constant also should exceed the stabili zation time for the high frequency oscillator 11 9 CLOCK A...

Page 55: ...he divisor used to obtain the high frequency System Clock from the PLL or Main Clock The divisor is FCDIV 1 MODE The PLL MODE field specifies the operation mode of the on chip PLL After reset the MODE bits are initialized to 100b so the PLL is configured to generate a 48 MHz clock This register must not be modified when the System Clock is derived from the PLL Clock The System Clock must be derive...

Page 56: ...lock can be the PLL Clock after a programmable divider or the 12 MHz Main Clock The activity of peripheral modules is controlled by their enable bits Power consumption can be reduced in this mode by selec tively disabling modules and by executing the WAIT instruc tion When the WAIT instruction is executed the CPU stops executing new instructions until it receives an interrupt sig nal After reset t...

Page 57: ...n the Bluetooth LLC is in Sleep mode Disable Bits The DMC and DHC bits in the PMMCR register may be used to disable the high frequency oscil lator and PLL respectively in Power Save and Idle modes When used to disable the high frequency oscilla tor or PLL the DMC and DHC bits override the HCC mechanism Power Management Mode Halt mode disables the high frequency oscillator and PLL Active Mode enabl...

Page 58: ...ent is detected 0 High frequency oscillator is only disabled in Halt mode or when disabled by the HCC mechanism 1 High frequency oscillator is also disabled in Power Save and Idle modes DHC The Disable High Frequency PLL Clock bit and the CRCTRL PLLPWD bit may be used to disable the PLL in Power Save and Idle modes When the DHC bit is clear and PLL PWD 0 the PLL is enabled in these modes If the DH...

Page 59: ...usually triggered by a hardware interrupt Figure 8 shows the four power consumption modes and the events that trigger a transition from one mode to another Figure 8 Power Mode State Diagram Some of the power up transitions are based on the occur rence of a wake up event An event of this type can be either a maskable interrupt or a non maskable interrupt NMI All of the maskable hardware wake up eve...

Page 60: ... to Active mode To enable the high frequency oscillator software writes a 0 to the PM MCR DMC bit Before writing a 0 to the PMMCR PSM bit software must first monitor the PMMSR OMC bit to deter mine when the oscillator has stabilized 12 7 6 Wake Up Transition to Active Mode A hardware wake up event switches the device directly from Power Save Idle or Halt mode to Active mode Hardware wake up events...

Page 61: ...ing to the corresponding inter rupt handler Therefore setting up the MIWU interrupt han dler is essential for any wake up operation Each 16 channel module has four interrupt requests that can be routed to the ICU as shown in Figure 9 Each of the 16 channels can be programmed to activate one of these four interrupt requests The 32 MIWU channels are named WUI0 through WUI31 as shown in Table 27 Each...

Page 62: ...n WK0EDG FF FC80h Wake Up Edge Detection Register Module 0 WK1EDG FF FCA0h Wake Up Edge Detection Register Module 1 WK0ENA FF FC82h Wake Up Enable Register Module 0 WK1ENA FF FCA2h Wake Up Enable Register Module 1 WK0ICTL1 FF FC84h Wake Up Interrupt Control Register 1 Module 0 WK1ICTL1 FF FCA4h Wake Up Interrupt Control Register 1 Module 1 WK0ICTL2 FF FC86h Wake Up Interrupt Control Register 2 Mod...

Page 63: ...rmat is shown below WKEN The Wake Up Enable bits enable and disable the MIWU channels The WKEN15 0 bits cor respond to the WUI15 0 channels respective ly 0 MIWU channel wake up events disabled 1 MIWU channel wake up events enabled 13 1 4 Wake Up 1 Enable Register WK1ENA The WK1ENA register is a word wide read write register that individually enables or disables wake up events from the MIWU channel...

Page 64: ...lects the interrupt request signal for the associated MIWU channels WUI15 8 At reset the WK2ICTL2 register is cleared which selects MIWU Interrupt Request 0 for all eight channels The register format is shown below WKINTR The Wake Up Interrupt Request Select fields select which of the four MIWU interrupt re quests are activated for the corresponding channel 00 Selects MIWU interrupt request 0 01 S...

Page 65: ...red 13 1 13 Wake Up Pending Clear Register WK0PCL The WK0PCL register is a word wide write only register that lets the CPU clear bits in the WKPND register Writing a 1 to a bit position in the WKPCL register clears the corre sponding bit in the WKPND register Writing a 0 has no ef fect Do not modify this register with instructions that access the register as a read modify write operand such as the...

Page 66: ...in the WK0PND and WK1PND registers 4 Set up the WK0ICTL1 WK1ICTL1 WK0ICTL2 and WK1ICTL2 registers to define the interrupt request sig nal used for each channel 5 Set the bits in the WK0ENA and WK1ENA registers corresponding to the wake up channels to be activated To change the edge sensitivity of a wake up channel use the following procedure Performing the steps in the order shown will prevent fal...

Page 67: ...output buffer is a TRI STATE buffer with weak pull up capability The weak pull up if used prevents the port pin from going to an undefined state when it operates as an input To reduce power consumption input buffers configured for general purpose I O are only enabled when they are read When configured for an alternate function the input buffers are enabled continuously To minimize power consumptio...

Page 68: ...trength Register PEALTS FF FCCCh Port E Alternate Function Select Register PFALT FF FCE0h Port F Alternate Function Register PFDIR FF FCE2h Port F Direction Register PFDIN FF FCE4h Port F Data Input Register PFDOUT FF FCE6h Port F Data Output Register PFWPU FF FCE8h Port F Weak Pull Up Register PFHDRV FF FCEAh Port F High Drive Strength Register PFALTS FF FCECh Port F Alternate Function Select Reg...

Page 69: ... or for output A clear bit in this register causes the corresponding pin to operate as an in put which puts the output buffer in the high impedance state A set bit causes the pin to operate as an output which enables the output buffer A reset operation clears the port direction registers which initializes the pins as inputs PxDIR The PxDIR bits select the direction of the cor responding port pin 0...

Page 70: ...e controlled independently PxALTS The PxALTS bits select among two alternate functions Table 30 shows the mapping of the PxALTS bits to the alternate functions Un used PxALTS bits must be clear 7 0 PxHDRV 7 0 PxALTS Table 30 Alternate Function Select Port Pin PxALTS 0 PxALTS 1 PE0 UART0 RXD0 Reserved PE1 UART0 TXD0 Reserved PE2 UART0 RTS Reserved PE3 UART0 CTS Reserved PE4 UART0 CKX TB PE5 SRFS NM...

Page 71: ... register PxDOUT and then use the port direction register PxDIR to set the value of the port pin With the direction register bit set direction out the value zero is forced on the pin With the direction register bit clear direction in the pin is placed in the TRI STATE mode If desired the internal weak pull up can be enabled to pull the signal high when the output buffer is in TRI STATE mode ...

Page 72: ...face signals are grouped as follows Modem Signals BBCLK RFDATA and RFSYNC Control Signal RFCE Serial Interface Signals SCLK SDAT and SLE Bluetooth Sequencer Status Signals BTSEQ1 BTSEQ2 and BTSEQ2 X1CKI BBCLK The X1CKI BBCLK pin is the input signal for the 12 MHz clock signal The radio chip uses this signal internally as the 12 oversampling clock and provides it externally to the CP3BT26 for use a...

Page 73: ...he PG4 pin to give control over this signal to the RF interface SLE The SLE pin is the serial load enable output of the serial in terface of the CP3BT26 During write operations to the radio chip registers the data received by the shift register of the radio chip is copied into the address register on the next rising edge of SCLK after the SLE signal goes high During read operations read from the r...

Page 74: ...e other than 101b and it is used to address the write only registers of the radio chip Fast writes load the same physical register as the corre sponding normal write operation For the power control and CMOS output registers of the RF chip it is only necessary to transmit a total of 8 bits 3 ad dress bits and 5 data bits because the remaining eight bits are unused While the FW bit is set normal Rea...

Page 75: ...he LMX5252 drives the counter value The counter value is 1 which indicates two words have been written SLE SCLK SDAT DS322 D16 D30 A0 A1 A2 A3 A4 W H0 H1 H2 D31 D0 D14 A0 A1 A2 A3 A4 W H0 H1 H2 D15 500 ns SLE SCLK SDAT DS323 D16 D31 A0 A1 A2 A3 A4 R H0 H1 H2 D0 D15 A0 A1 A2 A3 A4 R H0 H1 H2 500 ns Table 31 Example of 32 Bit Write with Interleaved Reads Cycle Serial Data on SDAT Description 1 101 0...

Page 76: ...ode all configura tion data is lost In this state the LMX5252 drives BPOR low Power Up When the power supply is on and the LMX5252 RESET input is high the LMX5252 starts up its crystal oscillator and enters Power Up mode After the crystal oscillator is settled the LMX5252 sends four clock cycles on BRCLK BBCLK before driving BPOR high RF Init The baseband controller on the CP3BT26 now drives RFCE ...

Page 77: ... starts counting After M 1 Slow Clock cycles the HCC signal to the PMM is deasserted 9 The PMM restarts the 12 MHz Main Clock and the PLL if required The N counter starts counting After N 1 Slow Clock cycles the Bluetooth clocks 1 MHz and 12 MHz are turned on again The Bluetooth se quencer starts operating 10 The Bluetooth sequencer waits for the completion of the sleep mode When completed the Blu...

Page 78: ...etooth LLC Ar bitration between these devices is performed in hardware Table 33 shows the memory map of the Bluetooth LLC shared Data RAM Table 33 Memory Map of Bluetooth Shared RAM Address offset from 0E 8000h Description 0000h 01D9h RF Programming Look up Table 01DAh 01FFh Unused 0200h 023Fh Link Control 0 0240h 027Fh Link Control 1 0280h 02BFh Link Control 2 02C0h 02FFh Link Control 3 0300h 033...

Page 79: ...between the output of the Input Multiplexer and the ADCIN external analog input 12 Bit ADC receives the output of the Internal External Multiplexer and performs the analog to digital conver sion ADCRESLT Register makes conversion results from the 12 Bit ADC available to the on chip bus The AD CRESLT register includes the software visible end of a 4 word FIFO used to queue conversion results The co...

Page 80: ...rsion data is lost The Done signal is visible to software as the ADC_DONE bit in the ADCRESLT register The Done signal is also an input to the interrupt controller IRQ13 The interrupt will be as serted whenever the FIFO is not empty but will deassert for one system clock after the ADCRESLT register is read To tal conversion time is around 15 microseconds The Done signal is also an input to the Mul...

Page 81: ...re used to produce one x y position coordinate pair To measure the x coordinate the TSX sig nal is pulled to VCC the TSX signal is pulled to GND and the TSY and TSY signals are undriven A voltage divider is formed across the X plate with the center tap of the divid er being the point of pen contact represented in Figure 26 by node A With TSY and TSY undriven the voltage at node A can be measured b...

Page 82: ...onal to the force of pen con tact 16 2 3 Compensation for Driver Resistance Plate resistances between opposite electrodes range from 100 ohms to 1k ohm Because of the 6 ohm driver resis tance some significant voltage drop will be experienced be tween for example TSX and AGND A 200 ohm plate will drop With a 2 5V supply this is 70 mV A 12 bit ADC has 4096 possible values so each value covers a rang...

Page 83: ...de is entered 3 ADC conversion completes and a wake up signal is as serted to the MIWU unit 4 Device wakes up and processes the conversion result To conserve power the ADC should be disabled before en tering a low power mode if its function is not required 16 4 FREEZE The ADC module provides support for an In System Emula tor by means of a special FREEZE input When FREEZE is asserted the module wi...

Page 84: ...ode 1 Differential mode MUX_CFG The Multiplexer Configuration field and the DIFF bit configure the analog circuits of the ADC module as shown in Table 35 For best noise immunity in touchscreen appli cations channel 2 should be used for sam pling the X plate voltage and channel 1 should be used for sampling the Y plate volt age TOUCH_CFG The Touchscreen Configuration field controls the configuratio...

Page 85: ...Y2 block to generate the ADC clock 0 ADC clock derived from System Clock 1 ADC clock derived from Auxiliary Clock 2 CLKDIV The Clock Divisor field specifies the divisor applied to System Clock to generate the 12 MHz clock required by the ADC module Only the System Clock is affected by this divisor The divisor is not used when Auxiliary Clock 2 is selected as the clock source PRM The ADC Primed bit...

Page 86: ...nversion Register ADCSTART The ADCSTART register is a write only register used by software to initiate an ADC conversion Writing any value to this register will cause the ADC to initiate a conversion or prime the ADC to initiate a conversion as controlled by the ADCCNTRL register 16 5 5 ADC Start Conversion Delay Register ADCSCDLY The ADCSCDLY register controls critical timing parameters for the o...

Page 87: ... sensed To enable pen down detection the TOUCH_CFG field of the ADCGCR register must be loaded with 101b When pen down detection is enabled and a pen down condition is sensed the PEN_DOWN bit is set This bit is not carried through the FIFO so its value represents the current status of the pen down detector When pen down detection is enabled the sig nal from the pen down detector is ORed with the D...

Page 88: ...the shift register from the System Clock When a new 16 bit word of random data is available it is loaded into the RNGD register If enabled an interrupt re quest IRQ3 is asserted when the word is available for reading When software reads the RNGD register the reg ister is cleared and the interrupt request is deasserted The RNGCST register provides control and status bits for the RNG module RNG Enab...

Page 89: ...ng the register it is cleared and the DVALID bit of the RNGCST register is cleared When a new word of valid random data becomes available in the RNGD register the DVALID bit is set and if enabled and interrupt request is asserted 17 2 3 RNG Divisor Register High RNGDIVH This register holds the two most significant bits of the RNGDIV clock divisor See the description of the RNGDIVL register 17 2 4 ...

Page 90: ...e bus activity The CR16 USB node looks for this event and signals it by setting the SD3 bit in the ALTEV register which causes an inter rupt to be generated if enabled Software should respond by putting the CR16 USB node in the NodeSuspend state The CR16 USB node can resume normal operation under software control in response to a local event in the device It can wake up the USB bus via a NodeResum...

Page 91: ...onal FIFOs are 64 bytes each for both transmit and receive Each FIFO can be programmed for one exclusive USB endpoint used together with one globally decoded USB function address Software must not enable both trans mit and receive FIFOs for endpoint zero at any given time Table 39 Endpoint FIFO Sizes If two endpoints in the same direction are programmed with the same endpoint number and both are e...

Page 92: ...e 31 Transmit FIFO Operation TFnS The Transmit FIFO n Size is the total number of bytes available within the FIFO TXRP The Transmit Read Pointer is incremented ev ery time the Endpoint Controller reads from the transmit FIFO This pointer wraps around to zero if TFnS is reached TXRP is never in cremented beyond the value of the write pointer TXWP An underrun condition occurs if TXRP equals TXWP and...

Page 93: ...RXFL is equal to or less than the number specified by the RFWL bit in the RXCn register RCOUNT The Receive FIFO Count indicates how many bytes can be read from the receive FIFO This value is accessible by software via the RXSn register 18 3 USB CONTROLLER REGISTERS The CR16 USB node has a set of memory mapped regis ters that can be read written from the CPU bus to control the USB interface Some re...

Page 94: ...int Control 6 Register TXS0 FF FDC4h Transmit Status 0 Register TXS1 FF FDD4h Transmit Status 1 Register TXS2 FF FDE4h Transmit Status 2 Register TXS3 FF FDF4h Transmit Status 3 Register TXC0 FF FDC6h Transmit Command 0 Register TXC1 FF FDD6 Transmit Command 1 Register TXC2 FF FDE6h Transmit Command 2 Register TXC3 FF FDF6h Transmit Command 3 Register TXD0 FF FDC2h Transmit Data 0 Register TXD1 FF...

Page 95: ... Reserved NFS Table 41 USB Functional States NFS Node State Description 00 NodeReset This is the USB Reset state This is entered upon a module reset or by software upon detection of a USB Reset Upon entry all endpoint pipes are disabled DEF in the Endpoint Control 0 EPC0 register and AD_EN in the Function Address FAR register should be cleared by software on entry to this state On exit DEF should ...

Page 96: ... is read 0 Frame timer has not entered an unlocked condition from a locked condition or re entered a locked condition from an un locked condition 1 Frame timer has either entered an un locked condition from a locked condition or re entered a locked condition from an unlocked condition RX_EV The Receive Event bit is set if any of the un masked bits in the Receive Event RXEV reg ister is set It indi...

Page 97: ...ume signalling detected 1 Resume signalling detected 18 3 6 Alternate Mask Register ALTMSK A set bit in the ALTMSK register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs Otherwise setting MAEV ALT bit is disabled The ALTMSK register is clear af ter reset It provides read write access from the CPU bus 18 3 7 Transmit Event Regis...

Page 98: ...of the RXEV register which cause the RX_EV bit in the MAEV register to be set When set and the corresponding bit in the RXEV register is set RX_EV bit in the MAEV register is set When clear the corresponding bit in the RXEV register does not cause the RX_EV bit to be set The RXMSK register pro vides read write access This register is clear after reset 18 3 11 NAK Event Register NAKEV A bit in the ...

Page 99: ... scribed below FN10 8 The Frame Number field holds the three most significant bits MSB of the current frame number received in the last SOF packet If a valid frame number is not received within 12060 bit times Frame Length Maximum FL MAX with tolerance of the previous change the frame number is incremented artificially If two successive frames are missed or are in correct the current FN is frozen ...

Page 100: ...AD_EN The Address Enable bit controls whether the AD field is used for address comparison If not the device does not respond to any token on the USB bus 0 The device does not respond to any token on the USB bus 1 The AD field is used for address compar ison 18 3 18 Control Register DMACNTRL The DMACNTRL register controls the main DMA functions of the CR16 USB node The DMACTRL register provides rea...

Page 101: ... bit set and the ACK_STAT bit not set If the AEH bit in the DMA Error Count DMAERR register is set the DERR bit is not set until DMAERRCNT in the DMAERR regis ter is cleared and another error is detected Errors are handled as specified in the DMAE RR register The DERR bit provides read ac cess and can only be written with a 0 from the CPU bus After reset this bit is cleared 0 No DMA error occurred...

Page 102: ...CNT The DMA Error Counter together with the au tomatic error handling feature defines the maximum number of consecutive bus errors before ADMA mode is stopped Software can set the 7 bit counter to a preset value Once ADMA is started the counter decrements from the preset value by 1 every time a bus er ror is detected Every successful transaction resets the counter back to the preset value When ADM...

Page 103: ... are set This bit allows read write access from the CPU bus After reset this bit is cleared 0 Disable STALL handshakes 1 Enable STALL handshakes 18 3 25 Transmit Status 0 Register TXS0 The TXS0 register reports the transmit status of the manda tory Endpoint 0 It is loaded with 08h after reset This regis ter allows read only access from the CPU bus TCOUNT The Transmission Count field indicates the ...

Page 104: ...ero length packets It is cleared when this register is read 0 No ACK was sent 1 An ACK was sent TOGGLE The Toggle bit reports the PID used when re ceiving the packet When clear this bit indi cates that the last successfully received packet had a DATA0 PID When set this bit in dicates that the packet had a DATA1 PID This bit is unchanged for zero length packets It is cleared when this register is r...

Page 105: ...evice does not respond to any address without regard to the EP_EN state 0 Address comparison is disabled 1 If the AD_EN bit is also set address com parison is enabled ISO When the Isochronous bit is set the endpoint is isochronous This implies that no NAK is sent if the endpoint is not ready but enabled i e if an IN token is received and no data is available in the FIFO to transmit or if an OUT to...

Page 106: ...us Zero length packets are indicated by setting this bit without writing any data to the FIFO The transmit state machine transmits the pay load data CRC16 and the EOP signal before clearing this bit 0 Last byte of the packet has not been writ ten to the FIFO 1 Last byte of the packet has been written to the FIFO TOGGLE The function of the Toggle bit differs depend ing on whether ISO or non ISO ope...

Page 107: ...o length OUT packet is received hardware contains two copies of this register One holds the receive status of a zero length packet and another holds the status of the next SETUP packet with data If a zero length packet is followed by a SETUP packet the first read of this register indicates the zero length packet status and the second read the SETUP packet status This register pro vides read only a...

Page 108: ...is complete 0 Writing 0 has no effect 1 Writing 1 flushes the FIFOs RFWL The Receive FIFO Warning Limit field speci fies how many more bytes can be received to the respective FIFO before an overrun condi tion occurs If the number of empty bytes re maining in the FIFO is equal to or less than the selected warning limit the RXWARN bit in the FWEV register is set 18 3 37 Receive Data Register n RXD E...

Page 109: ...th Programmable bit rate up to 1 Mbit s 15 message buffers each configurable as receive or transmit buffers Message buffers are 16 bit wide dual port RAM One buffer may be used as a BASIC CAN path Remote Frame support Automatic transmission after reception of a Remote Transmission Request RTR Auto receive after transmission of a RTR Acceptance filtering Two filtering capabilities global acceptance...

Page 110: ...d a Remote Frame It causes an other module either another master or a slave which ac cepts this remote frame to transmit a data frame after the remote frame has been completed Additional modules can be added to an existing network without a configuration change These modules can either perform completely new functions requiring new data or process existing data to perform a new functionality As th...

Page 111: ...d but without bit stuffing After five consecutive bits of the same value including in serted stuff bits a stuff bit of the inverted value is inserted into the bit stream by the transmitter and deleted by the re ceiver The following shows the stuffed and destuffed bit stream for consecutive ones and zeros 19 2 2 CAN Frame Fields Data and remote frames consist of the following bit fields Start of Fr...

Page 112: ...s the ACK slot and the ACK delimiter The ACK slot is filled with a recessive bit by the transmitter This bit is overwritten with a domi nant bit by every receiver that has received a correct CRC sequence The second bit of the ACK field is a recessive bit called the acknowledge delimiter The End of Frame field closes a data and a remote frame It consists of seven recessive bits 19 2 3 CAN Frame For...

Page 113: ...nded Arbitration Control Field Cyclic Redundancy Check Field CRC Acknowledgment field ACK End of Frame EOF Note that the DLC must have the same value as the corre sponding data frame to prevent contention on the bus The RTR bit is recessive STANDARD REMOTE FRAME number of bits 44 Control Field END OF FRAME CRC Field CRC Arbitration Field IDENTIFIER 10 0 11 START OF FRAME ID 10 ID0 ID3 RTR IDE RB0 ...

Page 114: ...for the delimiter The overload frame can only be sent after the end of frame EOF field and in this way destroys the fixed form of the in termission field As a result all other nodes also detect an overload condition and start the transmission of an overload flag After an overload flag has been transmitted the over load frame is closed by the overload delimiter Note The CAN module never initiates a...

Page 115: ...ror An acknowledgment error is detected whenever a transmit ting node does not get an acknowledgment from any other node i e when the transmitter does not receive a domi nant bit during the ACK frame Error States The device can be in one of five states with respect to error handling see Figure 43 Figure 43 Bus States Synchronize Once the CAN module is enabled it waits for 11 consecu tive recessive...

Page 116: ...f the REC is set the node is error passive and the REC will not increment any further The Error counters can be read by application software as described under CAN Error Counter Register CANEC on page 139 Special error handling for the TEC counter is performed in the following situations A stuff error occurs during arbitration when a transmitted recessive stuff bit is received as a dominant bit Th...

Page 117: ...he ideal waveform due to the physical conditions of the network bus length and load To compensate for the various delays with in a network the sample point can be positioned by pro gramming the length of TSEG1 and TSEG2 see Figure 44 In addition two types of synchronization are supported The BTL logic compares the incoming edge of a CAN bit with the internal bit timing The internal bit timing can ...

Page 118: ... as follows PSC PSC 5 0 2 TSEG1 TSEG1 3 0 1 TSEG2 TSEG2 2 0 1 Figure 47 CAN Prescaler 19 3 MESSAGE TRANSFER The CAN module has access to 15 independent message buffers which are memory mapped in RAM Each message buffer consists of 8 different 16 bit RAM locations and can be individually configured as a receive message buffer or as a transmit message buffer A dedicated acceptance filtering procedur...

Page 119: ...1 or 0 This provides the capability to accept only a single ID for each buffer or to accept a group of IDs The following two ex amples illustrate the difference Example 1 Acceptance of a Single Identifier If the global mask is loaded with 00h the acceptance filter ing of an incoming message is only determined by the indi vidual buffer ID This means that only one message ID is accepted for each buf...

Page 120: ...is the next to last bit of the EOF The re ceived identifier is then compared to every buffer ID together with the respective mask and the status As soon as the validation point is reached the whole contents of the hidden buffer are copied into the matching message buffer as shown in Figure 52 Note The hidden receive buffer must not be accessed by the CPU Figure 52 Receive Buffer The following sect...

Page 121: ...ry on page 127 Figure 53 shows the receive timing Figure 53 Receive Timing To indicate that a frame is waiting in the hidden buffer the BUSY bit ST 0 of the selected buffer is set during the copy procedure The BUSY bit will be cleared by the CAN module immediately after the data bytes are copied into the buffer After the copy process is finished the CAN module changes the status field to RX_FULL I...

Page 122: ...check for new messag es received during the read process from the buffer as this buffer is locked after the reception of the first valid frame A read from a locked receive buffer can be performed as shown in Figure 55 Figure 55 Buffer Read Routine BUFFLOCK Enabled For simplicity only the applicable interrupt routine is shown 1 Read the ID data and object control DLC RTR from the message buffer 2 W...

Page 123: ...TX_BUSY status the buffer is no longer ac cessible by the CPU except for the ST 3 1 bits of the CN STAT register Starting with the beginning of the CRC field of the current frame the CAN module looks for another buff er transmit request and selects the buffer with the highest priority for the next transmission by changing the buffer state from TX_ONCE to TX_BUSY This transmit request can be cancel...

Page 124: ...Load buffer identifier and data registers For remote frames the RTR bit of the identifier needs to be set and loading data bytes can be omitted 3 Configure the CNSTAT status field to the desired value TX_ONCE to trigger the transmission process of a single frame TX_ONCE_RTR to trigger the transmission of a sin gle data frame and then wait for a received remote frame to trigger consecutive data fra...

Page 125: ...nterrupt vector for all interrupt conditions In addition the data frame receive event is an input to the MIWU see Section 13 0 The inter rupt process can be initiated from the following sources CAN data transfer Reception of a valid data frame in the buffer Buffer state changes from RX_READY to RX_FULL or RX_OVERRUN Successful transmission of a data frame Buffer state changes from TX_ONCE to TX_NO...

Page 126: ...After processing all the receive interrupts software changes the CICEN register to disable all receive buffers and enable all transmit buffers then services all pending transmit buffer in terrupt requests according to their priorities 19 8 TIME STAMP COUNTER The CAN module features a free running 16 bit timer CT MR incrementing every bit time recognized on the CAN bus The value of this timer durin...

Page 127: ...bled All configuration and status registers can either be access ed by the CAN module or the CPU only These registers pro vide single cycle word and byte access without any potential wait state All register descriptions within the next sections have the fol lowing layout 19 9 2 Message Buffer Organization The message buffers are the communication interfaces be tween CAN and the CPU for the transmi...

Page 128: ...fer data is cur rently copied from the hidden buffer or if a message is scheduled for transmission or is currently transmitting The CAN module al ways clears this bit on a status update Table 51 CAN Controller Registers Name Address Description CNSTAT See Table 50 CAN Buffer Status Control Register CGCR 0E F100h CAN Global Configuration Register CTIM 0E F102h CAN Timing Register GMSKX 0E F104h Glo...

Page 129: ...dicates that software wrote TX_NOT_ACTIVE to a transmit buffer which is sched uled for transmission or is currently transmitting 1 1 0 0 TX_ONCE 1 1 0 1 TX_BUSY0 Indicates that a buffer is scheduled for trans mission or is actively transmitting it can be due to one of two cases a message is pending for transmission or is cur rently transmitting or an automated answer is pending for transmission or...

Page 130: ...ded Identifier IDE bit is clear The ID1 3 0 and ID0 15 0 bits are don t care bits A standard frame with eight data bytes is shown in Table 54 IDE The Identifier Extension bit determines wheth er the message is a standard frame or an ex tended frame 0 Message is a standard frame using 11 identifier bits 1 Message is an extended frame RTR The Remote Transmission Request bit indi cates whether the me...

Page 131: ...re if the buffer is configured to transmit a message with an extended identifier It will be received as monitored on the CAN bus IDE The Identifier Extension bit determines wheth er the message is a standard frame or an ex tended frame 0 Message is a standard frame using 11 identifier bits 1 Message is an extended frame RTR The Remote Transmission Request bit indi cates whether the message is a da...

Page 132: ... The Identifier Extension bit determines wheth er the message is a standard frame or an ex tended frame 0 Message is a standard frame using 11 identifier bits 1 Message is an extended frame RTR The Remote Transmission Request bit indi cates whether the message is a data frame or a remote frame 0 Message is a data frame 1 Message is a remote frame ID The ID field is used to build the 29 bit identif...

Page 133: ...cessive state is 0 BUFFLOCK The Buffer Lock bit configures the buffer lock function If this feature is enabled a buffer will be locked upon a successful frame reception The buffer will be unlocked again by writing RX_READY in the buffer status register i e after reading data 0 Lock function is disabled for all buffers 1 Lock function is enabled for all buffers TSTPEN The Time Sync Enable bit enabl...

Page 134: ... the transmitted frame is not ac knowledged by any other CAN node This fea ture can be used in conjunction with the LOOPBACK bit for stand alone tests outside of a CAN network 0 Normal mode 1 The CAN module does not expect to re ceive a dominant ACK bit to indicate the validity of a transmitted message LOOPBACK When the Loopback bit is set all messages sent by the CAN module can also be received b...

Page 135: ...t Pending Bit CIPND EIP ND is set and an error interrupt is generated if enabled by the Error Interrupt Enable CIEN EIEN 0 The EIPND bit is set on every error on the CAN bus 1 The EIPND bit is set only if the error state CSTPND NS changes as a result of in crementing either the receive or transmit error counter 19 10 7 CAN Timing Register CTIM The Can Timing Register CTIM defines the configuration...

Page 136: ...oming identifier bits When an extended frame is received from the CAN bus all GMSK bits GM 28 0 IDE RTR and XRTR are used to mask the incoming message In this case the RTR bit in the GMSK register corresponds to the SRR bit in the message The XRTR bit in the GMSK register corresponds to the RTR bit in the message During the reception of standard frames only the GMSK bits GM 28 18 RTR and IDE are u...

Page 137: ... the CAN module to interrupt the CPU if any kind of CAN receive transmit errors are detected This causes any error status change in the er ror counter registers REC TEC is able to gen erate an error interrupt 0 The error interrupt is disabled and no er ror interrupt will be generated 1 The error interrupt is enabled and a change in REC TEC will cause an inter rupt to be generated IEN The Buffer In...

Page 138: ...errupt code 1 Error interrupt pending is indicated in the interrupt code ICEN The Buffer Interrupt Code Enable bits control encoding for message buffer interrupts 0 Message buffer interrupt pending is not indicated in the interrupt code 1 Message buffer interrupt pending is indi cated in the interrupt code 19 10 14 CAN Status Pending Register CSTPND The CSTPND register holds the status of the CAN ...

Page 139: ...as the data field To calculate the bit position of the error the DLC of the message needs to be known For example for a DLC of 8 data bytes the bit counter starts with the value 8 8 1 63 so when EBID 5 0 111001b 57 then the bit number was 63 57 6 TXE The Transmit Error bit indicates whether the CAN module was an active transmitter at the time the error occurred 0 The CAN module was a receiver at t...

Page 140: ...e Disabling the CAN module also dis ables the CANRX pin As an alternative the CANRX pin can be connected to any other input pin of the Multi Input Wake Up module This input channel must then be configured to trigger a wake up event on a falling edge if a dominant bit is represented by a low level In this case the CAN module can be disabled before entering the reduced power mode After waking up sof...

Page 141: ...mum clock frequency in order to ensure proper functionality at various CAN bus speeds 19 11 4 Bit Time Logic Calculation Examples The calculation of the CAN bus clocks using CKI 16 MHz is shown in the following examples The desired baud rate for both examples is 1 Mbit s Example 1 PSC PSC 5 0 2 0 2 2 TSEG1 TSEG1 3 0 1 3 1 4 TSEG2 TSEG2 2 0 1 2 1 3 SJW TSEG2 3 Sample point positioned at 62 5 of bit...

Page 142: ...responding fil ter masks are set up in a way that the buffer is able to re ceive frames with the identifier ID_RX_TX The following sequence of events occurs 1 A message with the identifier ID_RX_TX from an other CAN node is received into the receive buffer 2 A message with the identifier ID_RX_TX is sent by the CAN module immediately after the reception took place When these conditions occur the f...

Page 143: ...s frame synchronization In asynchronous mode this signal is used as frame sync only by the transmitter In synchronous mode this signal is used as frame sync by both the transmitter and receiver The frame sync signal may be generated internally or it may be provided by an external source 20 1 4 Serial Receive Data SRD The SRD pin is used as an input when data is shifted into the Audio Receive Shift...

Page 144: ... O TXDSA0 0 all data to be transmitted is read from the transmit FIFO An IRQ is asserted as soon as the number data bytes or words available in the transmit FIFO is equal or less than a programmable warning limit DMA Support If the receiver interface is configured for DMA RXDSA0 1 received data is transferred from the ARSR into the DMA receive buffer 0 ARDR0 A DMA request is asserted when the ARDR...

Page 145: ... ARDRn reg ister is full If DMA is enabled for a transmit slot n TXDSAn 1 all data to be transmitted in slot n are read from the corresponding DMA transmit register ATDRn A DMA request is asserted to the DMA controller when the ATDRn register is empty Figure 68 illustrates the data flow for IRQ and DMA support in network mode using four slots per frame and DMA sup port enabled for slots 0 and 1 in...

Page 146: ...t 100 256 kHz 12 MHz 47 256 kHz 100 0 27 20 4 FRAME CLOCK GENERATION The clock for the frame synchronization signals is derived from the bit clock of the audio interface A 7 bit prescaler is used to divide the bit clock to generate the frame sync clock for the receive and transmit operations The bit clock is di vided by FCPRS 1 In other words the value software must write into the ACCR FCPRS field...

Page 147: ... to the FIFO was a write operation to the ATFR the FIFO is full If an additional write to ATFR is performed a transmit FIFO overrun occurs This error condition is not prevented by hardware Software must ensure that no transmit overrun occurs The transmit frame synchronization pulse on the SFS pin and the transmit shift clock on the SCK pin may be generat ed internally or they can be supplied by an...

Page 148: ...gister which were received during the assigned time slots A receive in terrupt or DMA request is initiated when this occurs DMA Operation When a complete data word has been received through the SRD pin in a slot n the new data word is transferred to the corresponding receive DMA register n ARDRn A DMA re quest is asserted when the ARDRn register is full If a new slot n data word is received while ...

Page 149: ...gister 20 6 3 Audio Control Data The audio interface provides the option to fill a 16 bit slot with up to three data bits if only 13 14 or 15 PCM data bits are transmitted These additional bits are called audio con trol data and are appended to the PCM data stream The AAI can be configured to append either 1 2 or 3 audio con trol bits to the PCM data stream The number of audio data bits to be used...

Page 150: ...the ISDN controller Figure 74 CP3BT26 ISDN Controller Connections To connect the AAI to an ISDN controller through an IOM 2 compatible interface the AAI needs to be configured in this way The AAI must be in IOM 2 Mode AGCR IOM2 1 The AAI operates in synchronous mode AGCR ASS 0 The AAI operates as a slave therefore the bit clock and frame sync source selection must be set to external ACGR IEFS 1 AC...

Page 151: ...registers are frozen will vary be cause they operate from a different clock than the one used to generate the freeze signal 20 7 AUDIO INTERFACE REGISTERS Table 67 Audio Interface Registers Name Address Description ARFR FF FD40h Audio Receive FIFO Register ARDR0 FF FD42h Audio Receive DMA Register 0 ARDR1 FF FD44h Audio Receive DMA Register 1 ARDR2 FF FD46h Audio Receive DMA Register 2 ARDR3 FF FD...

Page 152: ...io data word copied from ARSR In 8 bit mode the ARDH register holds undefined data 20 7 3 Audio Transmit FIFO Register ATFR The ATFR register shows the transmit FIFO location cur rently addressed by the Transmit FIFO Write Pointer TWP The Audio Transmit Shift Register ATSR receives 8 bit or 16 bit data from the transmit FIFO when the ATSR is empty In 8 bit mode only the lower 8 bit portion of the ...

Page 153: ...Select bit controls whether the interface receiver and transmitter uses long or short frame synchronization signals After reset the FSS bit is clear so short frame synchronization signals are used by default 0 Short bit length frame synchronization signal 1 Long word length frame synchronization signal IEBC The Internal External Bit Clock bit controls whether the bit clocks for receiver and trans ...

Page 154: ... transmit interrupt when the Transmit Buffer Almost Empty TX AE bit is set If the TXIE bit is clear no inter rupt will be generated 0 Transmit interrupt disabled 1 Transmit interrupt enabled TXEIE The Transmit Error Interrupt Enable bit con trols whether transmit error interrupts are gen erated Setting this bit to 1 enables a transmit error interrupt when the Transmit Buffer Un derrun TXUR bit is ...

Page 155: ...led 0 No overflow has occurred 1 Overflow has occurred RXSA The Receive Slot Assignment field specifies which slots are recognized by the receiver of the audio interface Multiple slots may be en abled If the frame consists of less than 4 slots the RXSA bits for unused slots are ig nored For example if a frame only consists of 2 slots RXSA bits 2 and 3 are ignored The following table shows the slot...

Page 156: ...rrun did not occur TXSA The Transmit Slot Assignment field specifies during which slots the transmitter is active and drives data through the STD pin The STD pin is in high impedance state during all other slots If the frame consists of less than 4 slots the TXSA bits for unused slots are ignored For example if a frame only consists of 2 slots TXSA bits 2 and 3 are ignored The fol lowing table sho...

Page 157: ...its After reset this register is clear RMD The Receive Master DMA field specify which slots audio channels are supported by DMA i e when a DMA request is asserted to the DMA controller If the RMDn bit is set for an assigned slot n RXDSAn 1 a DMA request n is asserted when the ARDRn is full If the RXDSAn bit for a slot is clear the RMDn bit is ignored The following table shows the receive DMA reque...

Page 158: ...ce If CVSD interrupts are enabled an interrupt is issued when either one of the CVSD FIFOs is almost empty or almost full On the PCM data side there is double buffering and on the CVSD side there is an eight word 8 16 bit FIFO for the read and write paths Inside the module a filter engine receives the 8 kHz stream of 16 bit samples and interpolates to generate a 64 kHz stream of 16 bit samples Thi...

Page 159: ...oftware must not use the CVNF bit as an indication of the number of valid words in the FIFO 21 5 CVSD TO PCM CONVERSION The converter core reads from the CVSD In FIFO every 250 µs and writes a new PCM sample into the PCMOUT buffer every 125 µs If the previous PCM data has not yet been transferred to the audio interface it will be overwritten with the new PCM sample If there are only three unread w...

Page 160: ...bit 15 repre sents the CVSD data bit at t t0 CVSDIN bit 0 represents the CVSD data bit at t t0 250 ms 21 9 2 CVSD Data Output Register CVSDOUT The CVSDOUT register is a 16 bit wide read only register It is used to read the CVSD data from the PCM to CVSD converter The FIFO is 8 words deep Reading the CVSD OUT register after reset returns undefined data 21 9 3 PCM Data Input Register PCMIN The PCMIN...

Page 161: ...ck enabled PCMINT The PCM Interrupt Enable bit controls gener ation of the PCM interrupt If set this bit en ables the PCM interrupt If the PCMINT bit is clear the PCM interrupt is disabled After re set this bit is clear 0 PCM interrupt disabled 1 PCM interrupt enabled CVSDINT The CVSD FIFO Interrupt Enable bit controls generation of the CVSD interrupt If set this bit enables the CVSD interrupt tha...

Page 162: ...uld be read If the CVSDINT bit is set an interrupt will be asserted when the CVNF bit is set If the DMACO bit is set a DMA request will be asserted when this bit is set Software must not rely on the CVNF bit as an indicator of the number of valid words in the FIFO Software must check the CVOUTST field to read the number of valid words in the FIFO The CVNF bit is cleared when the CVSTAT register is...

Page 163: ...circuit generates parity bits and checks for parity framing and overrun errors The Flow Control Logic block provides the capability for hardware handshaking between the UART and a peripheral device When the peripheral device needs to stop the flow of data from the UART it de asserts the clear to send CTS signal which causes the UART to pause after sending the current frame if any The UART asserts ...

Page 164: ...cter the contents of the RSFT register are copied into the UnRBUF register and the Receive Buffer Full bit URBF is set The URBF bit is automatically cleared when software reads the character from the URBUF register The RSFT register is not software accessible Figure 76 UART Block Diagram Figure 77 UART Asynchronous Communication TXD Transmitter Control and Error Detection Parity Generator Checker ...

Page 165: ... the CKX pin or the internal baud rate generator In the latter case the clock signal is placed on the CKX pin as an output 22 2 3 Attention Mode The Attention mode is available for networking this device with other processors This mode requires the 9 bit data for mat with no parity The number of start bits and number of stop bits are programmable In this mode two types of 9 bit characters are sent...

Page 166: ... factor of zero corresponds to no clock The no clock condition is the UART power down mode in which the UART clock is turned off to reduce power consumption Software must select the no clock condition before enter ing a new baud rate Otherwise it could cause incorrect data to be received or transmitted The UnPSR register must contain a value other than zero when an external clock is used at CKX 22...

Page 167: ...ed interrupts 22 2 8 DMA Support The UART module can operate with one or two DMA chan nels Two DMA channels must be used for processor inde pendent full duplex operation Both receive and transmit DMA can be enabled simultaneously If transmit DMA is enabled the UETD bit is set the UART generates a DMA request when the UTBE bit changes state from clear to set Enabling transmit DMA automatically dis ...

Page 168: ...ect Register 1 U1STAT FF F226h UART1 Status Register U1ICTRL FF F224h UART1 Interrupt Con trol Register U1OVR FF F230h UART1 Oversample Rate Register U1MDSL2 FF F232h UART1 Mode Select Register 2 U1SPOS FF F234h UART1 Sample Position Register U2RBUF FF F242h UART2 Receive Data Buffer U2TBUF FF F240h UART2 Transmit Data Buffer U2PSR FF F24Eh UART2 Baud Rate Prescaler U2BAUD FF F24Ch UART2 Baud Rate...

Page 169: ...e most significant bits are held in the UnPSR register The divisor value used is UDIV 10 0 1 22 3 5 UART Frame Select Register UnFRS The UnFRS register is a byte wide read write register that controls the frame format including the number of data bits number of stop bits and parity type This register is cleared upon reset The register format is shown below UCHAR The Character Frame Format field se...

Page 170: ...lly disables transmit interrupts without regard to the state of the UETI bit 0 Transmit DMA disabled 1 Transmit DMA enabled UERD The Enable Receive DMA bit controls whether DMA is used for UART receive operations Enabling receive DMA automatically disables receive interrupts without regard to the state of the UERI bit Receive error interrupts are unaffected by the UERD bit 0 Receive DMA disabled 1...

Page 171: ...e shift register to the UnRBUF register It is automatically cleared by the hardware when the UnRBUF register is read 0 Receive buffer is empty 1 Receive buffer is loaded UDCTS The Delta Clear To Send bit indicates whether the CTS input has changed state since the CPU last read this register This functionality is only available for the UART0 module 0 No change since last read 1 State has changed si...

Page 172: ...e three sam ples 22 4 BAUD RATE CALCULATIONS The UART baud rate is determined by the System Clock fre quency and the values in the UnOVR UnPSR and Un BAUD registers Unless the System Clock is an exact multiple of the baud rate there will be a small amount of er ror in the resulting baud rate 22 4 1 Asynchronous Mode The equation to calculate the baud rate in asynchronous mode is where BR is the ba...

Page 173: ...0 0 00 1800 7 401 9 5 0 00 8 1111 1 5 0 01 12 101 5 5 0 01 12 463 1 0 0 01 2000 16 1500 1 0 0 00 16 750 1 0 0 00 16 250 1 5 0 00 16 125 2 5 0 00 2400 16 1250 1 0 0 00 16 625 1 0 0 00 16 125 2 5 0 00 9 463 1 0 0 01 3600 8 1111 1 5 0 01 12 101 5 5 0 01 11 202 1 5 0 01 11 101 2 5 0 01 4800 16 625 1 0 0 00 16 125 2 5 0 00 10 250 1 0 0 00 7 119 2 5 0 04 7200 12 101 5 5 0 01 11 303 1 0 0 01 11 101 1 5 0...

Page 174: ... 16 11 4 1 0 1 36 10 1 3 5 0 79 128000 9 7 1 0 0 79 16 3 1 0 2 34 13 3 1 0 0 16 9 1 3 5 0 79 230400 10 1 3 5 0 79 13 2 1 0 0 16 11 2 1 0 1 36 7 1 2 5 0 79 345600 15 1 1 5 2 88 7 1 2 5 0 79 460800 7 1 2 5 0 79 13 1 1 0 0 16 576000 7 2 1 0 0 79 7 1 1 5 0 79 Baud Rate SYS_CLK 3 MHz SYS_CLK 2 MHz SYS_CLK 1 MHz SYS_CLK 500 kHz O N P err O N P err O N P err O N P err 300 16 250 2 5 0 00 12 101 5 5 0 01 ...

Page 175: ...erring 8 or 16 bits of data The master device supplies the synchronous clock MSK for the serial interface and initiates the data transfer The slave devices respond by sending or receiving the re quested data Each slave device uses the master s clock for serially shifting data out or in while the master shifts the data in or out The three wire system includes the serial data in signal MDIDO for mas...

Page 176: ...ch is transmitted on the MDODI pin master mode or the MDIDO pin slave mode is clocked out on the falling edge of the shift clock MSK The input data which is received via the MDIDO pin master mode or the MDODI pin slave mode is sampled on the rising edge of MSK In the alternate mode the output data is shifted out on the rising edge of MSK on the MDODI pin master mode or MDIDO pin slave mode The inp...

Page 177: ...ormal Mode SCIDL 1 Figure 87 Alternate Mode SCIDL 0 Figure 88 Alternate Mode SCIDL 1 Bit 0 LSB Bit 1 MSB 2 MSB 1 MSK End of Transfer Sample Point Shift Out Data Out MSB Bit 0 LSB Bit 1 MSB 2 MSB 1 Data In MSB DS069 Bit 0 LSB Bit 1 MSB 2 MSB 1 MSK End of Transfer Data Out MSB Bit 0 LSB Bit 1 MSB 2 MSB 1 Data In MSB Sample Point Shift Out DS070 Bit 0 LSB Bit 1 MSB 2 MSB 1 MSK End of Transfer Data Ou...

Page 178: ...transmitted on MDIDO is the data held in the MWDAT register regardless of its validity The master may negate the MWCS signal to synchronize the bit count between the master and the slave In the case that the slave is the only slave in the system MWCS can be tied to ground 23 4 INTERRUPT GENERATION Interrupts may be enabled for any of the conditions shown in Table 73 Figure 89 illustrates the inter...

Page 179: ...ve When clear the device operates as a slave When set the device operates as the master 0 CP3BT26 is slave 1 CP3BT26 is master MOD The Mode Select bit controls whether 8 or 16 bit mode is used When clear the device op erates in 8 bit mode When set the device op erates in 16 bit mode This bit must only be changed when the module is disabled or idle MWSTAT BSY 0 0 8 bit mode 1 16 bit mode ECHO The E...

Page 180: ...Register MWSTAT The MWSTAT register is a word wide read only register that shows the current status of the Microwire interface module At reset all non reserved bits are clear The regis ter format is shown below BSY The Busy bit when set indicates that the Mi crowire shifter is busy In master mode the BSY bit is set when the MWDAT register is written In slave mode the bit is set on the first leadin...

Page 181: ...transferred during each clock period Data is sampled during the high phase of the serial clock SCL Consequently throughout the clock high phase the data must remain stable see Figure 91 Any change on the SDA signal during the high phase of the SCL clock and in the middle of a transaction aborts the current transaction New data must be driven during the low phase of the SCL clock This protocol perm...

Page 182: ...this address with its own If there is a match the de vice considers itself addressed and sends an acknowledge signal Depending upon the state of the R W bit 1 read 0 write the device acts as a transmitter or a receiver The ACCESS bus protocol allows sending a general call ad dress to all slaves connected to the bus The first byte sent specifies the general call address 00h and the second byte spec...

Page 183: ...ict with other devices If a conflict is detected the transaction is aborted the ACBST BER bit is set and the ACBST MASTER bit is cleared 3 If the ACBCTL1 STASTRE bit is set and the transac tion was successfully completed i e both the ACB ST BER and ACBST NEGACK bits are cleared the ACBST STASTR bit is set In this case the ACB stalls any further ACCESS bus operations i e holds SCL low If the ACBCTL...

Page 184: ... recover the ACB becomes the bus master by issuing a Start Condition and sends an address field then issue a Stop Condition to synchronize all the slaves 24 2 2 Slave Mode A slave device waits in Idle mode for a master to initiate a bus transaction Whenever the ACB is enabled and it is not acting as a master i e ACBST MASTER 0 it acts as a slave device Once a Start Condition on the bus is detected...

Page 185: ...ttempt to access the register in other cases produces unpredictable results 24 3 2 ACB Status Register ACBST The ACBST register is a byte wide read only register that maintains current ACB status At reset and when the mod ule is disabled ACBST is cleared XMIT The Direction Bit bit is set when the ACB mod ule is currently in master slave transmit mode Otherwise it is cleared 0 Receive mode 1 Transm...

Page 186: ...24 3 3 ACB Control Status Register ACBCST The ACBCST register is a byte wide read write register that maintains current ACB status At reset and when the mod ule is disabled the non reserved bits of ACBCST are cleared BUSY The BUSY bit indicates that the ACB module is Generating a Start Condition In Master mode ACBST MASTER is set In Slave mode ACBCST MATCH or ACBCST GCMTCH is set In the period bet...

Page 187: ...module is disabled ACBCTL2 ENABLE 0 the ACBCTL1 register is cleared START The Start bit is set to generate a Start Condi tion on the ACCESS bus The START bit is cleared when the Start Condition is sent or upon detection of a Bus Error ACBST BER 1 This bit should be set only when in Master mode or when requesting Master mode If this device is not the active master of the bus ACBST MASTER 0 set ting...

Page 188: ... interrupts disabled 1 New match interrupts enabled STASTRE The Stall After Start Enable bit enables the stall after start mechanism When enabled the ACB is stalled after the address byte When the STASTRE bit is clear the ACB ST STASTR bit is always clear 0 No stall after start 1 Stall after start enabled 24 3 5 ACB Control Register 2 ACBCTL2 The ACBCTL2 register is a byte wide read write register...

Page 189: ...ing a request to become the bus master for the first time software should check that there is no activity on the bus by checking the BB bit after the bus allowed time out period When waking up from power down before checking the ACBCST MATCH bit test the ACBCST BUSY bit to make sure that the address transaction has finished The BB bit is intended to solve a deadlock in which two or more devices de...

Page 190: ...nter to receive buffer CALLS ACBStartX RETURNED error status UWORD ACBRead UBYTE Slave UWORD Addrs UWORD Count UBYTE buf ACB_T acb UBYTE err rcv UWORD Timeout acb ACB_T ACB_ADDRESS Set pointer to ACB module If the indicated address differs from the last if Addrs NextAddress recorded access i e Random Read we must first send a dummy write to the desired new address NextAddress Addrs Update last add...

Page 191: ... condition acb ACBctl1 ACBSTART Check if we re the Bus Master with timeout Timeout 100 while acb ACBst ACBSDAST Timeout Related to bus error problem if acb ACBst ACBBER If collision occurs clear error and return status acb ACBst ACBBER return ACBERR_COLLISION if Timeout If timeout we must NOT be the Master signal error return ACBERR_NOTMASTER Now send the address and R W flag acb ACBsda Slave R_nW...

Page 192: ...unts down on each rising edge of T0IN When the timer reaches zero it is automatically re loaded from the TWMT0 register and continues counting down from that value Therefore the frequency of the timer is When an external crystal oscillator is used as the SLCLK source or when the fast clock is divided accordingly fSLCLK is 32 768 kHz The value stored in TWMT0 can range from 0001h to FFFFh Figure 96...

Page 193: ...iguration TWCFG register is used to set the Watchdog configuration It controls the Watchdog clock source T0IN or T0OUT the type of Watchdog servicing using WDCNT or WDSDM and the locking state of the TWCFG TWCPR TIMER0 T0CSR and WDCNT registers A register that is locked cannot be read or written A write operation is ignored and a read op eration returns unpredictable results If the TWCFG register ...

Page 194: ...e Watchdog clock 0 Watchdog timer is clocked by T0OUT 1 Watchdog timer is clocked by T0IN WDSDME The Watchdog Service Data Match Enable bit controls which method is used to service the Watchdog timer When clear Watchdog ser vicing is accomplished by writing a count val ue to the WDCNT register write operations to the Watchdog Service Data Match WDSDM register are ignored When set Watchdog servicin...

Page 195: ...gister that holds the value that is loaded into the Watchdog counter each time the Watchdog is serviced The Watchdog is start ed by the first write to this register Each successive write to this register restarts the Watchdog count with the written value At reset this register is initialized to 0Fh 25 4 6 Watchdog Service Data Match Register WDSDM The WSDSM register is a byte wide write only regis...

Page 196: ...er units called Timer Counter 1 and Timer Counter 2 Figure 97 Multi Function Timer Block Diagram 26 1 1 Timer Counter Block The Timer Counter block contains the following functional blocks Two 16 bit counters Timer Counter 1 TCNT1 and Tim er Counter 2 TCNT2 Two 16 bit reload capture registers TCRA and TCRB Control logic necessary to configure the timer to operate in any of the four operating modes...

Page 197: ...lse accumulate mode is not available in the capture modes modes 2 and 4 because the TB pin is used as one of the two capture inputs Figure 99 Pulse Accumulate Mode Slow Clock The Slow Clock is generated by the Triple Clock and Reset module The clock source is either the divided fast clock or the external 32 768 kHz crystal oscillator if available and selected The Slow Clock can be used as the cloc...

Page 198: ...he timer can be configured to toggle the TA output bit on each underflow This generates a clock signal on the TA out put with the width and duty cycle determined by the values stored in the TCRA and TCRB registers This is a proces sor independent PWM clock because once the timer is set up no more action is required from the CPU to generate a continuous PWM signal The timer can be configured to gen...

Page 199: ...es reflect the elapsed time between transitions on the TA pin The same is true for the TCRB register and the TB pin The input signal on the TA or TB pin must have a pulse width equal to or greater than one System Clock cycle There are three separate interrupts associated with the cap ture timer each with its own enable bit and pending bit The three interrupt events are reception of a transition on...

Page 200: ...own from the reloaded val ue In addition the TA pin is toggled on each underflow if this function is enabled by the TAEN bit The initial state of the TA pin is software programmable When the TA pin is tog gled from low to high it sets the TCPND interrupt pending bit and also generates an interrupt if enabled by the TAIEN bit Because the TA pin toggles on every underflow a 50 duty cycle PWM signal ...

Page 201: ...RB register The input pin can be configured to sense ei ther rising or falling edges The TB input can be configured to preset the counter to FFFFh on reception of a valid capture event In this case the current value of the counter is transferred to the capture register and then the counter is preset to FFFFh The values captured in the TCRB register at different times reflect the elapsed time betwe...

Page 202: ...For example to start with TA high software must set the TAOUT bit before en abling the timer clock This option is available only when the timer is configured to operate in Mode 1 3 or 4 in other words when TCRA is not used in Capture mode Table 77 Timer Interrupts Overview Sys Int Interrupt Pending Bit Mode 1 Mode 2 Mode 3 Mode 4 PWM Counter Dual Input Capture Counter Dual Counter Single Capture C...

Page 203: ...served 110 Reserved 111 Reserved C2CSEL The Counter 2 Clock Select field specifies the clock mode for Timer Counter 2 as follows 000 No clock Timer Counter 2 stopped modes 1 2 and 3 only 001 Prescaled System Clock 010 External event on TB modes 1 and 3 only 011 Pulse accumulate mode based on TB modes 1 and 3 only 100 Slow Clock 101 Reserved 110 Reserved 111 Reserved Operation of the Slow Clock is ...

Page 204: ... is enabled to operate as a preset input or as a PWM output depending on the timer operat ing mode In Mode 2 Dual Input Capture a transition on the TA pin presets the TCNT1 counter to FFFFh In the other modes TA functions as a PWM output When this bit is clear operation of the pin for the timer counter is disabled 0 TA input disabled 1 TA input enabled TBEN The TB Enable bit controls whether the T...

Page 205: ...controls whether an interrupt is generated on each oc currence of interrupt condition A For an ex planation of interrupt conditions A B C and D see Table 77 0 Condition A interrupts disabled 1 Condition A interrupts enabled TBIEN The Timer Interrupt B Enable bit controls whether an interrupt is generated on each oc currence of interrupt condition B For an ex planation of interrupt conditions A B C...

Page 206: ... each with a separate in terrupt pending bit and interrupt enable bit 27 1 VTU FUNCTIONAL DESCRIPTION The VTU is comprised of four timer subsystems Each timer subsystem contains an 8 bit clock prescaler a 16 bit up counter and two 16 bit registers Each timer subsystem controls two I O pins which either function as PWM outputs or capture inputs depending on the mode of operation There are four syst...

Page 207: ... TIOx output will remain at the default value which corre sponds to a duty cycle of 0 in which case the value in the PERCAPx register is irrelevant This scheme allows the duty cycle to be programmed in a range from 0 to 100 In order to allow fully synchronized updates of the period and duty cycle compare values the PERCAPx and DTY CAPx registers are double buffered when operating in PWM mode There...

Page 208: ...erating in 16 bit PWM mode The numbering in Figure 107 refers to timer subsystem 1 but equally applies to the other three timer subsystems Figure 107 VTU 16 bit PWM Mode 27 1 3 Dual 16 Bit Capture Mode In addition to the two PWM modes each timer subsystem may be configured to operate in an input capture mode which provides two 16 bit capture channels The input cap ture mode can be used to precisel...

Page 209: ...e four timer subsystems Figure 109 illustrates the interrupt structure of the versatile timer module Figure 109 VTU Interrupt Request Structure Each of the timer pending bits IxAPD through IxDPD is set by a specific hardware event depending on the mode of operation i e PWM or Capture mode Table 80 outlines the specific hardware events relative to the operation mode which cause an interrupt pending...

Page 210: ...it counter may individually be started or stopped via its associated TxRUN bit The TIOx pins will function as PWM out puts 10 16 bit PWM mode The two 8 bit counters are concatenated to form a sin gle 16 bit counter The counter may be started or stopped with the lower of the two TxRUN bits i e T1RUN T3RUN T5RUN and T7RUN The TIOx pins will function as PWM outputs 11 Capture Mode Both 8 bit counters...

Page 211: ... described in the IO1CTL register sec tion 27 2 4 Interrupt Control Register INTCTL The INTCTL register is a word wide read write register It contains the interrupt enable bits for all 16 interrupt sources of the VTU Each interrupt enable bit corresponds to an in terrupt pending bit located in the Interrupt Pending Register INTPND All INTCTL register bits are solely under soft ware control The reg...

Page 212: ...errupt condition for the related timer subsystem has occurred Table 80 on page 209 lists the hardware condition which causes this bit to be set 0 No interrupt pending 1 Timer interrupt condition occurred 27 2 6 Clock Prescaler Register 1 CLK1PS The CLK1PS register is a word wide read write register The register is split into two 8 bit fields called C1PRSC and C2PRSC Each field holds the 8 bit cloc...

Page 213: ...written while the counter is running the write will not take effect until counter value matches the pre vious period compare value or until the counter is stopped Reading may take place at any time and will return the most recent value which was written The PERCAPx registers are cleared at reset 27 2 10 Duty Cycle Capture Register n DTYCAPx The Duty Cycle Capture DTYCAPx registers are word wide re...

Page 214: ...write a read only register will have unpredictable results When software writes to a register in which one or more bits are reserved it must write a zero to each reserved bit unless indicated otherwise in the description of the register Read ing a reserved bit returns an undefined value Table 82 Detailed Device Mapping Register Name Size Address Access Type Value After Reset Comments Bluetooth LLC...

Page 215: ...MER_ADJUST_MINUS Byte 0E F1C7h Read Only SLOTTIMER_WR_RD Byte 0E F1C8h Read Only USB Node Registers MCNTRL Byte FF FD80h Read Write 00h FAR Byte FF FD88h Read Write 00h NFSR Byte FF FD8Ah Read Write 00h MAEV Byte FF FD8Ch Read Write 00h MAMSK Byte FF FD8Eh Read Write 00h ALTEV Byte FF FD90h Read Write 00h ALTMSK Byte FF FD92h Read Write 00h TXEV Byte FF FD94h Read Write 00h TXMSK Byte FF FD96h Rea...

Page 216: ...6h Read Write 00h EPC2 Byte FF FDD8h Read Write 00h RXD1 Byte FF FDDAh Read Write XXh RXS1 Byte FF FDDCh Read Write 00h RXC1 Byte FF FDDEh Read Write 00h EPC3 Byte FF FDE0h Read Write 00h TXD2 Byte FF FDE2h Read Write XXh TXS2 Byte FF FDE4h Read Write 1Fh TXC2 Byte FF FDE6h Read Write 00h EPC4 Byte FF FDE8h Read Write 00h RXD2 Byte FF FDEAh Read Write XXh RXS2 Byte FF FDECh Read Write 00h RXC2 Byt...

Page 217: ...Xh Same register layout as CMB0 CMB5 8 word 0E F050h 0E F05Fh Read Write XXXXh Same register layout as CMB0 CMB6 8 word 0E F060h 0E F06Fh Read Write XXXXh Same register layout as CMB0 CMB7 8 word 0E F070h 0E F07Fh Read Write XXXXh Same register layout as CMB0 CMB8 8 word 0E F080h 0E F08Fh Read Write XXXXh Same register layout as CMB0 CMB9 8 word 0E F090h 0E F09Fh Read Write XXXXh Same register lay...

Page 218: ... Word 0E F118h Read Only 0000h CTMR Word 0E F11Ah Read Only 0000h DMA Controller ADCA0 Double Word FF F800h Read Write 0000 0000h ADRA0 Double Word FF F804h Read Write 0000 0000h ADCB0 Double Word FF F808h Read Write 0000 0000h ADRB0 Double Word FF F80Ch Read Write 0000 0000h BLTC0 Word FF F810h Read Write 0000h BLTR0 Word FF F814h Read Write 0000h DMACNTL0 Word FF F81Ch Read Write 0000h DMASTAT0 ...

Page 219: ...h Read Write 0000h DMASTAT2 Byte FF F85Eh Read Write 00h ADCA3 Double Word FF F860h Read Write 0000 0000h ADRA3 Double Word FF F864h Read Write 0000 0000h ADCB3 Double Word FF F868h Read Write 0000 0000h ADRB3 Double Word FF F86Ch Read Write 0000 0000h BLTC3 Word FF F870h Read Write 0000h BLTR3 Word FF F874h Read Write 0000h DMACNTL3 Word FF F87Ch Read Write 0000h DMASTAT3 Byte FF F87Eh Read Write...

Page 220: ...d Write 18h FMTRAN Byte FF F954h Read Write 30h FMPROG Byte FF F956h Read Write 16h FMPERASE Byte FF F958h Read Write 04h FMMERASE0 Byte FF F95Ah Read Write EAh FMEND Byte FF F95Eh Read Write 18h FMMEND Byte FF F960h Read Write 3Ch FMRCV Byte FF F962h Read Write 04h FMAR0 Word FF F964h Read Only FMAR1 Word FF F966h Read Only FMAR2 Word FF F968h Read Only Flash Data Memory Interface FSMIBAR Word FF...

Page 221: ...T Word FF FC26h Read Only 0000h LOGIN Byte FF FC28h Write Only 0000h LOGOUT Byte FF FC2Ah Read Only 0000h LINEARIN Word FF FC2Ch Write Only 0000h LINEAROUT Word FF FC2Eh Read Only 0000h CVCTRL Word FF FC30h Read Write 0000h CVSTAT Word FF FC32h Read Only 0000h CVTEST Word FF FC34h Read Write 0000h CVRADD Word FF FC36h Read Write 0000h CVRDAT Word FF FC38h Read Write 0000h CVDECOUT Word FF FC3Ah Re...

Page 222: ...1EDG Word FF FCA0h Read Write 00h WK1ENA Word FF FCA2h Read Write 00h WK1ICTL1 Word FF FCA4h Read Write 00h WK1ICTL2 Word FF FCA6h Read Write 00h WK1PND Word FF FCA8h Read Write 00h Bits may only be set writing 0 has no effect WK1PCL Word FF FCAAh Write Only XXh WK1IENA Word FF FCACh Read Write 00h General Purpose I O Ports PBALT Byte FF FB00h Read Write 00h PBDIR Byte FF FB02h Read Write 00h PBDI...

Page 223: ...d Only XXh PFDOUT Byte FF FCE6h Read Write XXh PFWPU Byte FF FCE8h Read Write 00h PFHDRV Byte FF FCEAh Read Write 00h PFALTS Byte FF FCECh Read Write 00h PGALT Byte FF F300h Read Write 00h PGDIR Byte FF F302h Read Write 00h PGDIN Byte FF F304h Read Only XXh PGDOUT Byte FF F306h Read Write XXh PGWPU Byte FF F308h Read Write 00h PGHDRV Byte FF F30Ah Read Write 00h PGALTS Byte FF F30Ch Read Write 00h...

Page 224: ...2 Word FF FD50h Write Only 0000h ATDR3 Word FF FD52h Write Only 0000h AGCR Word FF FD54h Read Write 0000h AISCR Word FF FD56h Read Write 0000h ARSCR Word FF FD58h Read Write 0004h ATSCR Word FF FD5Ah Read Write F003h ACCR Word FF FD5Ch Read Write 0000h ADMACR Word FF FD5Eh Read Write 0000h Interrupt Control Unit IVCT Byte FF FE00h Read Only 10h Fixed Addr NMISTAT Byte FF FE02h Read Only 00h EXNMI ...

Page 225: ...0Ch Read Write 00h U0PSR Byte FF F20Eh Read Write 00h U0OVR Byte FF F210h Read Write 00h U0MDSL2 Byte FF F212h Read Write 00h U0SPOS Byte FF F214h Read Write 06h UART1 U1TBUF Byte FF F220h Read Write XXh U1RBUF Byte FF F222h Read Only XXh U1ICTRL Byte FF F224h Read Write 01h Bits 0 1 read only U1STAT Byte FF F226h Read only 00h U1FRS Byte FF F228h Read Write 00h U1MDSL1 Byte FF F22Ah Read Write 00...

Page 226: ...Write 00h U2MDSL2 Byte FF F252h Read Write 00h U2SPOS Byte FF F254h Read Write 06h UART3 U3TBUF Byte FF F260h Read Write XXh U3RBUF Byte FF F262h Read Only XXh U3ICTRL Byte FF F264h Read Write 01h Bits 0 1 read only U3STAT Byte FF F266h Read only 00h U3FRS Byte FF F268h Read Write 00h U3MDSL1 Byte FF F26Ah Read Write 00h U3BAUD Byte FF F26Ch Read Write 00h U3PSR Byte FF F26Eh Read Write 00h U3OVR ...

Page 227: ...ite 00h TWCP Byte FF FF22h Read Write 00h TWMT0 Word FF FF24h Read Write FFFFh T0CSR Byte FF FF26h Read Write 00h WDCNT Byte FF FF28h Write Only 0Fh WDSDM Byte FF FF2Ah Write Only 5Fh Multi Function Timer TCNT1 Word FF FF40h Read Write XXh TCRA Word FF FF42h Read Write XXh TCRB Word FF FF44h Read Write XXh TCNT2 Word FF FF46h Read Write XXh TPRSC Byte FF FF48h Read Write 00h TCKC Byte FF FF4Ah Rea...

Page 228: ... 0000h COUNT3 Word FF FF9Ah Read Write 0000h PERCAP3 Word FF FF9Ch Read Write 0000h DTYCAP3 Word FF FF9Eh Read Write 0000h COUNT4 Word FF FFA0h Read Write 0000h PERCAP4 Word FF FFA2h Read Write 0000h DTYCAP4 Word FF FFA4h Read Write 0000h ADC ADCGCR Word FF F3C0h Read Write 0000h ADCACR Word FF F3C2h Read Write 0000h ADCCNTRL Word FF F3C4h Read Write 0000h ADCSTART Word FF F3C6h Write Only N A ADC...

Page 229: ...BT26 RNG RNGCST Word FF F280h Read Write 0000h RNGD Word FF F282h Read Write 0000h RNGDIVH Word FF F284h Read Write 0000h RNGDIVL Word FF F286h Read Write 0000h Register Name Size Address Access Type Value After Reset Comments ...

Page 230: ...erved RX_CN 6 0 TX_CN Reserved TX_CN 6 0 AC_ACCEPTLVL 7 0 AC_ACCEPTLVL 7 0 AC_ACCEPTLVL 15 8 Reserved AC_ACCEPTLVL 9 8 LAP_ACCEPTLVL Reserved LAP_ACCEPTLVL 5 0 RFSYNCH_DELAY Reserved RFSYNCH_DELAY 5 0 SPI_READ 7 0 SPI_READ 7 0 SPI_READ 15 8 SPI_READ 15 8 SPI_MODE_CONFIG Reserved SPI_CLK_CONF 1 0 SPI_LEN_ CONF SPI_DATA _CONF3 SPI_DATA _CONF2 SPI_DATA_ CONF1 M_COUNTER_0 M_COUNTER 7 0 M_COUNTER_1 M_C...

Page 231: ..._TIMER_STATUS_ EXP_FLAG LINK_TIMER_STATUS_EXP_FLAG 7 0 LINK_TIMER_STATUS_ RD_WR_FLAG Reserved LINK_ TIMER _WRITE_ DONE LINK_ TIMER_ READ_ VALID LINK_TIMER_ADJUST_ PLUS LINKTIMER_ADJUST_PLUS 7 0 LINK_TIMER_ADJUST_ MINUS LINKTIMER_ADJUST_MINUS 7 0 SLOTTIMER_WR_RD Reserved SLOT_TIMER_WR_RD 5 0 Bluetooth LLC Registers 7 6 5 4 3 2 1 0 USB Registers 7 6 5 4 3 2 1 0 MCNTRL Reserved HOS NAT HALT Reserved ...

Page 232: ...X_DONE TCOUNT TXC0 Red IGN_IN FLUSH TOGGLE Reserved TX_EN RXD0 RXFD RXS0 Res SETUP TOGGLE RX_LAST RCOUNT RXC0 Reserved FLUSH IGN_ SETUP IGN_OUT RX_EN EPC1 STALL Reserved ISO EP_EN EP TXD1 TXFD TXS1 TX_URUN ACK_STAT TX_DONE TCOUNT TXC1 IGN_ ISOMSK TFWL RFF FLUSH TOGGLE LAST TX_EN EPC2 STALL Reserved ISO EP_EN EP RXD1 RXFD RXS1 RX_ERR SETUP TOGGLE RX_LAST RCOUNT RXC1 Reserved RFWL Res FLUSH IGN_ SET...

Page 233: ... FLUSH IGN_ SETUP Reserved RX_EN USB Registers 7 6 5 4 3 2 1 0 CAN Control Status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CGCR Reserved EIT DIAG EN INTE RNAL LOOP BACK IGN ACK LO DD IR TST PEN BUFF LOCK CRX CTX CAN EN CTIM PSC 6 0 SJW 1 0 TSEG1 3 0 TSEG2 2 0 GMSKB GM 28 18 RTR IDE GM 17 15 GMSKX GM 14 0 XRTR BMSKB BM 28 18 RTR IDE BM 17 15 BMSKX BM 14 0 XRTR CIEN EI EN IEN 14 0 CIPND EI PND IPND 14 ...

Page 234: ... 5 7 Data 5 6 Data 5 5 Data 5 4 Data 5 3 Data 5 2 Data 5 1 Data 5 0 Data 6 7 Data 6 6 Data 6 5 Data 6 4 Data 6 3 Data 6 2 Data 6 1 Data 6 0 CMBn DATA3 Data 7 7 Data 7 6 Data 7 5 Data 7 4 Data 7 3 Data 7 2 Data 7 1 Data 7 0 Data 8 7 Data 8 6 Data 8 5 Data 8 4 Data 8 3 Data 8 2 Data 8 1 Data 8 0 CMBn TSTP TSTP 15 TSTP 14 TSTP 13 TSTP 12 TSTP 11 TSTP 10 TSTP 9 TSTP 8 TSTP 7 TSTP 6 TSTP 5 TSTP 4 TSTP ...

Page 235: ...CFG0 Reserved FRE IPRE IPST Res BW WBR RBE HOLD WAIT SZCFG1 Reserved FRE IPRE IPST Res BW WBR RBE HOLD WAIT SZCFG2 Reserved FRE IPRE IPST Res BW WBR RBE HOLD WAIT TBI Register 7 6 5 4 3 2 1 0 TMODE Reserved TSTEN ENMEM TMSEL Flash Program Memory Interface Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMIBAR Reserved IBA FMIBDR IBD FM0WER FM0WE FM1WER FM1WE FM2WER FM2WE FM3WER FM3WE FMCTRL Reserv...

Page 236: ... 8 7 6 5 4 3 2 1 0 Flash Data Memory Interface Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSMIBAR Reserved IBA FSMIBDR IBD FSM0WER FM0WE FSM1WER FM1WE FSM2WER FM2WE FSM3WER FM3WE FSMCTRL Reserved MER PER PE IENP ROG DIS VRF Res CWD LOW PRW FSMSTAT Reserved DE RR FM FULL FM BUSY PE RR EE RR FSMPSR Reserved FTDIV FSMSTART Reserved FTSTART FSMTRAN Reserved FTTRAN FSMPROG Reserved FTPROG FSMPERAS...

Page 237: ...served LOGIN LOGOUT Reserved LOGOUT LINEARIN LINEARIN LINEAROUT LINEAROUT CVCTRL Reserved PCM CO NV CVSD CONV DMA PI DMA PO DMA CI DMA CO CVS DER RINT CVS DINT PCM INT CLK EN CV EN CVSTAT Reserved CVOUTST CVINST CVF CVE PCM INT CVN F CV NE CVTEST Reserved TEST _VAL ENC _IN DEC _EN RT TB CVRADD Reserved CVRADD CVRDAT CVRDAT CVDECOUT CVDECOUT CVENCIN CVENCIN CVENCPR CVENCPRT CLK3RES Registers 7 6 5 ...

Page 238: ...R11 WKINTR10 WKINTR9 WKINTR8 WKPND WKPD WKPCL WKCL WKIENA WKIEN GPIO Registers 7 6 5 4 3 2 1 0 PxALT Px Pins Alternate Function Enable PxDIR Px Port Direction PxDIN Px Port Output Data PxDOUT Px Port Input Data PxWPU Px Port Weak Pull Up Enable PxHDRV Px Port High Drive Strength Enable PxALTS Px Pins Alternate Function Source Selection AAI Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARSR ARSH ...

Page 239: ...ed ACO ACD TMD RMD AAI Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICU Registers 15 12 11 8 7 6 5 4 3 2 1 0 IVCT Reserved 0 0 INTVECT 5 0 ISTAT0 IST 15 0 ISTAT1 IST 31 16 IENAM0 IENA 15 0 IENAM1 IENA 31 16 UART Registers 7 6 5 4 3 2 1 0 UnTBUF UnTBUF UnRBUF URBUF UnICTRL UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE UnSTAT Reserved UXMIP URB9 UBKD UERR UDOE UFE UPE UnFRS Reserved UPEN UPSEL UXB9 U...

Page 240: ...0 ENABLE ACBADDR2 SAEN ADDR ACBCTL3 Reserved ARPEN SCLFRQ 8 7 TWM Registers 15 8 7 6 5 4 3 2 1 0 TWCFG Reserved Reserved WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG TWCP Reserved Reserved MDIV TWMT0 PRESET T0CSR Reserved Reserved FRZT0E WDTLD T0INTE TC RST WDCNT Reserved PRESET WDSDM Reserved RSTDATA MFT16 Registers 15 8 7 6 5 4 3 2 1 0 TCNT1 TCNT1 TCRA TCRA TCRB TCRB TCNT2 TCNT2 TPRSC Reserved Reser...

Page 241: ...BPD I4APD I3DPD I3CPD I3BPD I3APD I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD CLK1PS C2PRSC C1PRSC COUNT1 CNT1 PERCAP1 PCAP1 DTYCAP1 DCAP1 COUNT2 CNT2 PERCAP2 PCAP2 DTYCAP2 DCAP2 CLK2PS C4PRSC C3PRSC COUNT3 CNT3 PERCAP3 PCAP3 DTYCAP3 DCAP3 COUNT4 CNT4 PERCAP4 PCAP4 DTYCAP4 DCAP4 ADC Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCGCR MUX OUTEN INTEN Res NREF_CFG PREF_CFG TOUCH_CFG MUX_CFG D...

Page 242: ...www national com 242 CP3BT26 RNG Registers 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RNGCST Reserved IMSK Reserved DVALID RNGE RNGD RNGD RNGDIVH Reserved RNGDIV17 16 RNGDIVL RNGDIV15 0 ...

Page 243: ...25 2 75 V IOVcc I O Supply Voltage 2 25 3 63 V AVcc Analog PLL Supply Voltage 2 25 2 75 V ADVcc ADC Supply Voltage 2 25 2 75 V UVcc USB Supply Voltage 3 0 3 63 V VIL Logical 0 Input Voltage except X1CKI X2CKI and RESET 0 5 0 3 Vcc V VIH Logical 1 Input Voltage except X1CKI X2CKI and RESET 0 7 IOVcc IOVcc 0 5 V Vxl1 X1CKI Logical 0 Input Voltage External X1 clock 0 5 0 3 Vcc V Vxh1 X1CKI Logical 1 ...

Page 244: ... 2 mA Iccq Digital Supply Current Halt Mode e f Vcc 2 75V IOVcc 3 63V 20 C 150 µA a Guaranteed by design b Run from internal memory RAM Iout 0 mA X1CKI 12 MHz PLL enabled 4 internal system clock is 24 MHz not programming Flash memory c Same conditions as Icca1 but programming or erasing Flash memory page d Running from internal memory RAM Iout 0 mA XCKI1 12 MHz PLL disabled X2CKI 32 768 kHz device...

Page 245: ... 3V 10 10 µA CTRN Transceiver Capacitance 20 pF Symbol Parameter Conditions Min Typ Max Units VPREF ADC Positive Reference Input 2 2 75 V VNREF ADC Negative Reference Input 0 0 25 V ADC Input Range VNREF VPREF V Clock Frequency 12 MHz tC Conversion Time 12 bit result 14 µs INL Integral Non Linearity 2 LSB DNL Differential Non Linearity 0 7 LSB CADCIN Total Capacitance of ADC Input 9 20 pF CADCINS ...

Page 246: ...MPER ASE register 20 ms tMERASE Module Erase Pulse Widthe e Module Erase Pulse Width is determined by the following equation tMERASE Tclk FTDIV 1 4096 FTMER 1 where Tclk is the System Clock period FTDIV is the contents of the FMPSR or FSMPSR register and FTMER is the contents of the FMMERASE0 or FSMMERASE0 register 200 ms tEND NVSTR Hold Timef f NVSTR Hold Time is determined by the following equat...

Page 247: ...RI STATE Previous state PG7 0 TRI STATE Previous state PH7 0 TRI STATE Previous state PJ7 0 TRI STATE Previous state Table 84 Clock and Reset Signals Symbol Figure Description Reference Min ns Max ns Clock Input Signals tX1p 110 X1 period Rising Edge RE on X1 to next RE on X1 83 33 83 33 tX1h 110 X1 high time external clock At 2V level Both Edges 0 5 Tclk 5 tX1l 110 X1 low time external clock At 0...

Page 248: ...igure 110 Clock Timing Figure 111 NMI Signal Timing Figure 112 Non Power On Reset Figure 113 Power On Reset X1CKI tX1h tX1l tX1p X2CKI tX2h tX2l tX2p DS095 CLK tIW tlH tlS NMI DS096 CLK tRST RESET DS097 VCC 0 9 VCC 0 1 VCC t DS115 R ...

Page 249: ...nput Signals tIs 114 Input setup time RXD asynchronous mode Before Rising Edge RE on CLK tIh 114 Input hold time RXD asynchronous mode After RE on CLK UART Output Signals tCOv1 114 TXD output valid all signals with propagation delay from CLK RE After RE on CLK tTXD 114 TXD output valid After RE on CLK 40 CLK TXD RXD 1 tCOv1 tlS tlH tCOv1 1 1 2 2 2 1 1 1 2 2 2 DS098 ...

Page 250: ... O Port Input Signals tIS 115 Input Setup Time Before Rising Edge RE on System Clock tIH 115 Input Hold Time After RE on System Clock I O Port Output Signals tCOv1 115 Output Valid Time After RE on System Clock tOF 115 Output Floating Time After RE on System Clock CLK 1 1 1 2 2 2 1 1 1 2 2 2 PORTS B C input PORTS B C output tIS tCOv1 tlH tCOv1 tOF DS100 ...

Page 251: ... Rising Edge RE on SRCLK 20 tFSH 116 Frame Sync Hold Time After RE on SRCLK 20 AAI Output Signals tCP 116 Receive Transmit Clock Period RE on SRCLK SCK to RE on SRCLK SCK 976 6 tCL 116 Receive Transmit Low Time FE on SRCLK SCK to RE on SRCLK SCK 488 3 tCH 116 Receive Transmit High Time RE on SRCLK SCK to FE on SRCLK SCK 488 3 tFSVH 116 118 Frame Sync Valid High RE on SRCLK SCK to RE on SRFS SFS 20...

Page 252: ... Transmit Timing Short Frame Sync Figure 118 Receive Timing Long Frame Sync Figure 119 Transmit Timing Long Frame Sync 0 STD SCK SFS DS117 1 0 1 2 tTDV 0 SRD SRCLK SRFS DS118 1 0 1 2 tFSVH tFSVL tRDH tRDS N 0 STD SCK SFS DS119 1 0 1 2 tTDV N ...

Page 253: ... 1 Before FE MSK tMDIh 120 Microwire Data In Hold master Normal Mode After RE MSK 0 122 Alternate Mode After FE MSK 120 Microwire Data In Hold slave Normal Mode After RE MSK 40 122 Alternate Mode After FE MSK tMDIs 120 Microwire Data In Setup Normal Mode Before RE MSK 80 122 Alternate Mode Before FE MSK Microwire SPI Output Signals tMSKh 120 Microwire Clock High At 2 0V both edges 40 tMSKl 120 Mic...

Page 254: ...fter RE on MSK tMITOp 124 MDODI to MDIDO slave only Propagation Time Value is the same in all clocking modes of the Microwire 25 Table 88 Microwire SPI Signals Symbol Figure Description Reference Min ns Max ns lsb msb tMSKp tMSKh tMDlh tMSKd tMCSs tMCSh tMDls tMSKs tMDOf tMDOv tMDOff tMDOh tMSKhd Data In lsb msb MDODI master msb lsb MDIDO slave MSK MCS slave tMSKl DS101 ...

Page 255: ...CP3BT26 Figure 121 Microwire Transaction Timing Normal Mode SCIDL 1 lsb msb tMSKp tMSKh tMDlh tMDls tMCSs tMCSh tMSKs tMDOf tMDOv tMDOf tMDOh Data In MSK lsb msb MDODO master lsb msb MDIDO slave tMSKh MCS slave tMSKhd DS102 ...

Page 256: ...3BT26 Figure 122 Microwire Transaction Timing Alternate Mode SCIDL 0 MSK lsb msb Data In lsb msb MDODO master lsb msb MDIDO slave MCS slave tMSKp tMSKh tMDlh tMDls tMCSs tMCSh tMSKs tMDOf tMDOv tMDOf tMDOh tMSKl tMSKhd DS103 ...

Page 257: ...t Normal Mode SCIDL 0 ECHO 1 Slave Mode lsb msb tMSKp tMSKh tMDlh tMDls tMCSs tSKd tMCSh tMSKs tMDOf tMDOv tMDOff tMDOh Data In MSK lsb msb MDODI master lsb msb MDIDO slave tMSKh MCS slave only tMSKhd DS104 MSK Dl lsb Dl msb MDODI slave DO lsb DO msb MDIDO slave MCS tMSKp tMSKh tMDlh tMDls tMCSs tMCSh tMSKs tMDOnf tMITOp tMITOp tMDOf tMSKl tMSKhd DS105 ...

Page 258: ...tCLK tSDAri 125 SDA signal rise time 1000 tSDAfl 125 SDA signal fall time 300 tSDAhi 128 SDA hold time After SCL FE 0 tSDAsi 128 SDA setup time Before SCL RE 2 tCLK ACCESS bus Output Signals tBUFo 126 Bus free time between Stop and Start Condition tSCLhigho tCSTOso 126 SCL setup time Before Stop Condition tSCLhigho tCSTRho 126 SCL hold time After Start Condition tSCLhigho tCSTRso 127 SCL setup tim...

Page 259: ...for input signal timing 0 3VCC tSCLf 0 7VCC 0 3VCC tSCLr SDA 0 7VCC 0 3VCC tSDAf 0 7VCC 0 3VCC tSDAr DS106 SCL SDA tDLCs tCSTOs tCSTRh Stop Condition Start Condition tBUF Note In the timing tables the parameter name is added with an o for output signal timing and i for input signal timing DS107 SCL SDA tDHCs tCSTRs Start Condition tCSTRh Note In the timing tables the parameter name is added with a...

Page 260: ...128 ACB Data Timing tSCAvo tSDAh tCSLlow tSDAsi tSCLhigh SCL SDA Note In the timing tables the parameter name is added with an o for output signal timing and i for input signal timing unless the parameter already includes the suffix DS109 ...

Page 261: ...RFM Fall Rise Time Matching TR TF CL 50 pF 90 110 VCRS Output Signal Crossover Voltage CL 50 pF 1 3 2 0 V ZDRV Driver Output Impedance CL 50 pF 28 43 ohms a Waveforms measured at 10 to 90 Table 91 Multi Function Timer Input Signals Symbol Figure Description Reference Min ns Max ns tTAH 129 TA High Time Rising Edge RE on CLK TCLK 5 tTAL 129 TA Low Time RE on CLK TCLK 5 tTBH 129 TB High Time RE on C...

Page 262: ...0 Versatile Timing Unit Input Timing Table 92 Versatile Timing Unit Input Signals Symbol Figur e Description Reference Min ns Max ns tTIOH 129 TIOx Input High Time Rising Edge RE on CLK 1 5 TCLK 5ns tTIOL 129 TIOx Input Low Time RE on CLK 1 5 TCLK 5ns tTIOL tTIOH CLK TIOx DS110 ...

Page 263: ... 0 After RE on CLK 8 t5 131 132 133 134 135 Output Active Inactive Time RD SEL 1 0 SELIO After RE on CLK 8 t6 131 132 Output Active Inactive Time WR 1 0 After RE on CLK 0 5 Tclk 8 t7 133 Minimum Inactive Time RD At 2 0V Tclk 4 t8 131 Output Float Time D 15 0 After RE on CLK 8 t9 131 Minimum Delay Time From RD Trailing Edge TE to D 15 0 driven Tclk 4 t10 131 132 Minimum Delay Time From RD TE to SEL...

Page 264: ...en Normal Read Cycles No Wait States T1 T2 T1 T2 T3 T1 T2 A 21 0 A22 13 only CLK Normal Read Normal Read Early Write SELx D 15 0 In In Out t4 t4 t12 SELy y x RD WR 1 0 t5 t12 t5 t12 t5 t12 t8 t12 t3 t9 t5 t12 t5 t12 t6 t13 t5 t12 t6 t13 t2 t1 Bus State DS124 ...

Page 265: ...Normal Read Cycles No Wait States T1 T2 T1 T2 T1 T2 CLK SELx D 15 0 In In Out y x RD Normal Read Normal Read Late Write t4 t12 t5 t12 t5 t12 t5 t12 t5 t12 t8 t12 t3 t11 t5 t12 t6 t13 t6 t13 t5 t12 t10 t9 t4 t12 SELy y x WR 1 0 A 21 0 A22 13 only Bus State DS125 ...

Page 266: ...tive Normal Read Cycles Burst No Wait States T1 T2 T2B T1 T2 T2B Normal Read Normal Read CLK SELx SELy WR 1 0 D 15 0 In In In In y x y x RD t5 t12 t5 t12 t4 t12 t4 t12 t4 t5 t12 t5 t12 t7 t5 t12 t5 t12 t2 t1 t2 t1 A 21 0 A22 13 only Bus State DS126 ...

Page 267: ...w national com CP3BT26 Figure 134 Normal Read Cycle Wait Cycle Followed by Hold Cycle T1 TW T2 TH CLK D 15 0 SELn SELIO WR 1 0 RD t4 t5 t12 t5 t12 t5 t12 t5 t12 t2 t1 t4 t12 A21 0 A22 13 only Bus State DS127 ...

Page 268: ...gure 135 Early Write Between Fast Read Cycles Tidle T1 2 T1 T1 T2 T3 T1 2 Fast Read Early Write CLK SELx SELy WR 1 0 D 15 0 y x y x RD Fast Read t5 t12 t5 t12 t2 t1 t5 t12 t5 t12 t4 t12 t4 A 21 0 A22 13 only Bus State DS128 In In Out ...

Page 269: ...EQ3 TA IOGND PE4 CKX TB PJ3 WUI21 39 TDI TMS RESET ADC7 ADCIN ADC6 ADC5 MUXOUT1 ADC4 MUXOUT0 ADC3 TSY ADC2 TSX ADC1 TSY ADC0 TSX VREF ADGND ADVCC PE3 CTS PE0 RXD0 PE2 RTS GND VCC PE1 TXD0 SDA SCL IOVCC IOGND VCC GND IOGND IOVCC IOVCC PG5 SLE PG4 SDAT PG3 SCLK PG1 RFCE PG0 RFSYNC RFDATA IOGND PJ6 WUI24 PJ5 WUI23 65 TCK PJ7 ASYNC WUI9 PH0 RXD1 WUI11 TDO IOVCC RDY PF3 MWCS TIO4 IOGND PF0 MSK TIO1 GND...

Page 270: ... SDA 82 I O ADC0 TSX 92 I O HIZ 20mA ADC1 TSY 93 I O HIZ 20mA ADC2 TSX 94 I O HIZ 20mA ADC3 TSY 95 I O HIZ 20mA ADC4 MUXOUT0 96 I O ADC5 MUXOUT1 97 I O ADC6 98 I ADC7 ADCIN 99 I VREFP 91 I PB0 D0 23 GPIO PB1 D1 22 GPIO PB2 D2 20 GPIO PB3 D3 19 GPIO PB4 D4 18 GPIO PB5 D5 16 GPIO PB6 D6 15 GPIO PB7 D7 14 GPIO PC0 D8 12 GPIO PC1 D9 11 GPIO PC2 D10 9 GPIO PC3 D11 8 GPIO PC4 D12 6 GPIO Table 94 Pin Ass...

Page 271: ...GPIO PG6 WUI10 37 GPIO PG7 TA 41 GPIO PH0 RXD1 WUI11 105 GPIO PH1 TXD1 WUI12 46 GPIO PH2 RXD2 WUI13 48 GPIO PH3 TXD2 WUI14 50 GPIO PH4 RXD3 WUI15 52 GPIO PH5 TXD3 WUI16 54 GPIO PH6 CANRX WUI17 57 GPIO PH7 CANTX 59 GPIO PJ0 WUI18 128 GPIO PJ1 WUI19 1 GPIO PJ2 WUI20 38 GPIO PJ3 WUI21 39 GPIO PJ4 WUI22 64 GPIO PJ5 WUI23 65 GPIO PJ6 WUI24 66 GPIO PJ7 ASYNC WUI9 104 GPIO Note 1 The ENV0 ENV1 ENV2 RESET...

Page 272: ... WUI17 PH5 TXD3 WUI16 IOGND A19 A18 PH4 RXD3 WUI15 IOVCC PH3 TXD2 WUI14 IOGND VCC PH2 RXD2 WUI13 37 TDI TMS RESET ADC7 ADCIN ADC6 ADC5 MUXOUT1 ADC4 MUXOUT0 ADC3 TSY ADC2 TSX ADC1 TSY ADC0 TSX VREF ADGND ADVCC PE3 CTS PE0 RXD0 PE2 RTS GND VCC PE1 TXD0 SDA SCL VCC GND IOGND SELIO SEL2 SEL1 IOVCC PG5 SLE PG4 SDAT PG3 SCLK PG1 RFCE PG0 RFSYNC RFDATA 73 TCK PJ7 ASYNC WUI9 PH0 RXD1 WUI11 TDO PF0 MSK TIO...

Page 273: ...CC 95 PWR UVCC 71 PWR UGND 72 PWR X1CKI BBCLK 26 I X1CKO 25 O X2CKI 29 I X2CKO 30 O ENV2 SLOWCLK 33 I O ENV1 CPUCLK 34 I O ENV0 PLLCLK 35 I O RESET 106 I TMS 107 I TDI 108 I TCK 109 I TDO 112 O RDY 113 O RFDATA 73 I O D 70 I O D 69 I O SCL 87 I O SDA 88 I O ADC0 TSX 98 I O HIZ 20mA ADC1 TSY 99 I O HIZ 20mA ADC2 TSX 100 I O HIZ 20mA ADC3 TSY 101 I O HIZ 20mA ADC4 MUXOUT0 102 I O ADC5 MUXOUT1 103 I ...

Page 274: ...IO2 123 GPIO PF2 MDODI TIO3 127 GPIO PF3 MWCS TIO4 115 GPIO PF4 SCK TIO5 135 GPIO PF5 SFS TIO6 136 GPIO PF6 STD TIO7 137 GPIO PF7 SRD TIO8 138 GPIO PG0 RFSYNC 74 GPIO PG1 RFCE 75 GPIO PG2 SRCLK 133 GPIO PG3 SCLK 76 GPIO PG4 SDAT 77 GPIO PG5 SLE 78 GPIO PG6 WUI10 36 GPIO PG7 TA 38 GPIO PH0 RXD1 WUI11 111 GPIO PH1 TXD1 WUI12 47 GPIO PH2 RXD2 WUI13 48 GPIO PH3 TXD2 WUI14 50 GPIO PH4 RXD3 WUI15 52 GPI...

Page 275: ...A6 128 O A5 125 O A4 124 O A3 119 O A2 118 O A1 116 O A0 114 O SEL0 79 O SEL1 81 O SEL2 82 O SELIO 83 O RD 65 O WR0 67 O WR1 68 O Note 1 The ENV0 ENV1 ENV2 RESET TCK TDI and TMS pins each have a weak pull up to keep the input from floating Note 2 These functions are always enabled due to the direct low impedance path to these pins Pin Name Alternate Function s Pin Number Type ...

Page 276: ...ule Updated layout of Bluetooth LLC registers Added usage hint for avoiding ACCESS bus module bus error Added usage hint for avoiding CAN unexpected loopback condition 2 28 04 Changed NSID designations in the product selection guide Updated Bluetooth section for LMX5251 and LMX5252 radio chips Added BTSEQ 3 1 signals to pin descriptions GPIO alternate functions and package pin assignments Added en...

Page 277: ...277 www national com CP3BT26 33 0 Physical Dimensions millimeters unless otherwise noted Figure 138 LQFP 128 Package Figure 139 LQFP 144 Package ...

Page 278: ...HOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to per form when properly used in accordance with instructions for use provided in the labeling can be reasonably ex...

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