F u n c tio n a l D e s c rip tio n
(Continued)
CONTROL/STATUS BITS
WDREN: WD Reset Enable
WDUDF: WATCHDOG Timer Underflow Bit
This bit resides in the CNTRL2 Register. The bit is set when
the WATCHDOG timer underflows. The underflow resets
the device if the WATCHDOG reset enable bit is set
(WDREN = 1). Otherwise, WDUDF can be used as the tim
er underflow flag. The bit is cleared upon Brown-Out reset,
external reset, load to the 8-bit counter, or going into the
HALT mode. It is a read only bit.
WDREN bit resides in a separate register (bit 0 of WDREG).
This bit enables the WATCHDOG timer to generate a reset.
The bit is cleared upon Brown Out reset, or external reset.
The bit under software control can be written to only once
(once written to, the hardware does not allow the bit to be
changed during program execution).
WDREN = 1 WATCHDOG reset is enabled.
WDREN = 0 WATCHDOG reset is disabled.
Table VI shows the impact of Brown Out Reset, WATCH
DOG Reset, and External Reset on the Control/Status bits.
INTERNAL DATA BUS
TL/DD/11208-15
FIGURE 12. WATCHDOG Timer Block Diagram
1-63
COP820CJ
/COP
822
CJ/C
OP8
23C
J
