COP8
20C
J/CO
P8
22C
J/CO
P82
3CJ
T im e r /C o u n te r
(Continued)
MODE 3. TIMER WITH CAPTURE REGISTER
Tinner T1 can be used to precisely measure external fre
quencies or events in this mode of operation. The timer T1
counts down at the instruction cycle rate. Upon the occur
rence of a specified edge on the TIO pin the contents of the
timer T1 are copied into the register R1. Bits in the control
register CNTRL allow the trigger edge to be specified either
as a positive edge or as a negative edge. In this mode the
user can elect to be interrupted on the specified trigger
edge
(Figure 10).
T L /D D /1 1 2 0 8 -2 5
FIGURE 10. Timer Capture Mode Block Diagram
TIMER PWM APPLICATION
Figure 11
shows how a minimal component D/A converter
can be built out of the Timer-Register pair in the Auto-Re
load mode. The timer is placed in the “ Timer with auto re
load” mode and the TIO pin is selected as the timer output.
At the outset the TIO pin is set high, the timer T1 holds the
on time and the register R1 holds the signal off time. Setting
TRUN bit starts the timer which counts down at the instruc
tion cycle rate. The underflow toggles the TIO output and
copies the off time into the timer, which continues to run. By
alternately loading in the on time and the off time at each
successive interrupt a PWM frequency can be easily gener
ated.
'
if_r
l
A SIMPLE D - A
CONVERTER USING
THE TIMER TO
GENERATE A PWM
OUTPUT.
T L /D D /1 1 208-26
FIGURE 11. Timer Application
W a tc h d o g
The device has an on-board 8-bit WATCHDOG timer. The
timer contains an 8-bit READ/WRITE down counter clocked
by an 8-bit prescaler. Under software control the timer can
be dedicated for the WATCHDOG or used as a general pur
pose counter.
Figure 12
shows the WATCHDOG timer block
diagram.
MODE 1: WATCHDOG TIMER
The WATCHDOG is designed to detect user programs get
ting stuck in infinite loops resulting in loss of program con
trol or “ runaway” programs. The WATCHDOG can be en
abled or disabled (only once) after the device is reset as a
result of brown out reset or external reset. On power-up the
WATCHDOG is disabled. The WATCHDOG is enabled by
writing a"“ 1” to WDREN bit (resides in WDREG register).
Once enabled, the user program should write periodically
into the 8-bit counter before the counter underflows. The
8-bit counter (WDCNT) is memory mapped at address OCE
Hex. The counter is loaded with n-1 to get n counts. The
counter underflow resets the device, but does not disable
the WATCHDOG. Loading the 8-bit counter initializes the
prescaler with FF Hex and starts the prescaler/counter.
Prescaler and counter are stopped upon counter underflow.
Prescaler and counter are each loaded with FF Hex when
the device goes into the HALT mode. The prescaler is used
for crystal/resonator start-up when the device exits the
HALT mode through Multi-Input Wakeup. In this case, the
prescaler/counter contents are changed.
MODE 2: TIMER
In this mode, the prescaler/counter is used as a timer by
keeping the WDREN (WATCHDOG reset enable) bit at 0.
The counter underflow sets the WDUDF (underflow) bit and
the underflow does not reset the device. Loading the 8-bit
counter (load n-1 for n counts) sets the WDTEN bit
(WATCHDOG Timer Enable) to “ 1” , loads the prescaler
with FF, and starts the timer. The counter underflow stops
the timer. The WDTEN bit serves as a start bit for the
WATCHDOG timer. This bit is set when the 8-bit counter is
loaded by the user program. The load could be as a result of
WATCHDOG service (WATCHDOG timer dedicated for
WATCHDOG function) or write to the counter (WATCHDOG
timer used as a general purpose counter). The bit is cleared
upon Brown Out reset, WATCHDOG reset or external reset,
th e bit is not memory mapped and is transparent to the
user program.
TABLE VI. WATCHDOG Control/Status
Parameter
HALT
Mode
WD
Reset
EXT/BOR
Reset
(Note 1)
Counter
Load
8-Bit Prescaler
FF
f f
FF
FF
8-Bit WD Counter
FF
FF
FF
User Value
WDREN Bit
Unchanged
Unchanged
:
0
No Effect
WDUDF Bit
0
Unchanged
0
0
WDTEN Signal
Unchanged
0
0
1
Note 1:
B O R is B ro w n O u t R eset.
1-62
