COP820CJ
/COP
822
CJ/C
OP8
23C
J
C o m p a ra to r
The device has one differential comparator. Ports L0-L2
are used for the comparator. The output of the comparator
is brought out to a pin. Port L has the following assignments:
LO Comparator output
L1 Comparator negative input
L2 Comparator positive input
THE COMPARATOR STATUS/CONTROL BITS
These bits reside in the CNTRL2 Register (Address OCC)
CMPEN
Enables comparator (“ 1” = enable)
CMPRD
Reads comparator output internally
(CMPEN = 1, CMPOE = X)
CMPOE
Enables comparator output to pin LO
("1" = enable), CMPEN bit must be set to en
able this function. If CMPEN = 0, LO will be 0.
The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power the program
should also disable the comparator before the device enters
the HALT mode.
The user program must set up LO, L1 and L2 ports correctly
for comparator Inputs/Output: L1 and L2 need to be config
ured as inputs and LO as output.
M u lti-In p u t W a k e Up
The Multi-Input Wakeup feature is used to return (wakeup)
the device from the HALT mode.
Figure 16
shows the Multi-
Input Wakeup logic.
This feature utilizes the L Port. The user selects which par
ticular L port bit or combination of L Port bits will cause the
device to exit the HALT mode. Three 8-bit memory mapped
registers, Reg:WKEN, Reg:WKEDG, and Reg:WKPND are
used in conjunction with the L port to implement the Multi-
Input Wakeup feature.
All
three
registers
Reg:WKEN,
Reg.WKPND,
and
Reg:WKEDG are read/write registers, and are cleared at
reset, except WKPND. WKPND is unknown on reset.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg:WKEDG, which is an 8-
bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose
we wish to change the edge select from positive (low going
high) to negative (high going low) for L port bit 5, where bit 5
has previously been enabled for an input. The program
would be as follows:
RBIT 5,WKEN
SBIT 5,WKEDG
RBIT 5,WKPND
SBIT 5,WKEN
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup, a safety proce
dure should also be followed to avoid inherited pseudo
wakeup conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared. This
same procedure should be used following RESET, since the
L port inputs are left floating as a result of RESET.
The occurrence of the selected trigger condition for Multi-In
put Wakeup is latched into a pending register called
Reg:WKPND. The respective bits of the WKPND register
will be set on the occurrence of the selected trigger edge on
the corresponding Port L pin. The user has the responsibility
of clearing these pending flags. Since the Reg:WKPND is a
pending register for the occurrence of selected wakeup
conditions, the device will not enter the HALT mode if any
Wakeup bit is both enabled and pending. Setting the G7
data bit under this condition will not allow the device to en
ter the HALT mode. Consequently, the user has the respon
sibility of clearing the pending flags before attempting to
enter the HALT mode.
If a crystal oscillator is being used, the Wakeup signal will
not start the chip running immediately since crystal oscilla
tors have a finite start up time. The WATCHDOG timer pre
scaler generates a fixed delay to ensure that the oscillator
has indeed stabilized before allowing the device to execute
instructions. In this case, upon detecting a valid Wakeup
signal only the oscillator circuitry and the WATCHDOG timer
are enabled. The WATCHDOG timer prescaler is loaded
with a value of FF Hex (256 counts) and is clocked from the
tc instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on chip inverter ensures that the WATCH
DOG timer is clocked only when the oscillator has a suffi
ciently large amplitude to meet the Schmitt trigger specs.
This Schmitt trigger is not part of the oscillator closed loop.
The startup timeout from the WATCHDOG timer enables
the clock signals to be routed to the rest of the chip.
1-66
