C O P 8 2 0 C J Pin A s s ig n m e n t
Port
Pin
Typ
ALT
Funct.
16
Pin
20
Pin
28
Pin
LO
I/O
MIWU/CMPOUT
5
7
11
L1
I/O
MIWU/CMPIN-
6
8
12
L2
I/O
MIWU/CMPIN +
7
9
13
L3
I/O
MIWU
8
10
14
L4
I/O
MIWU
9
11
15
L5
I/O
MIWU
10
12
16
L6
I/O
MIWU
11
13
17
L7
I/O
MIWU/MODOUT
12
14
18
GO
I/O
INTR
17
25
G1
I/O
18
26
G2
I/O
19
27
G3
I/O
TIO
15
20
28
G4
I/O
SO
1
1
G5
I/O
SK
16
2
2
G6
I
SI
1
3
3
G7
I
CKO
2
4
4
I0
I
7
11
I
8
I2
I
9
I3
I
10
DO
0
19
D1
0
20
D2
0
21
D3
o
22
Vcc
4
6
6
GND
13
15
23
CKI
3
5
5
RESET
14
16
24
Pin D e s c rip tio n
Vcc and GND
are the power supply pins.
CKI
is the clock input. This can come from an external
source, a R/C generated oscillator or a crystal (in conjunc
tion with CKO). See Oscillator description.
RESET
is the master reset input. See Reset description.
PORT I
is a 4-bit Hi-Z input port.
PORT L
is an 8-bit I/O port.
There are two registers associated with the L port: a data
register and a configuration register. Therefore, each L
I/O bit can be individually configured under software control
as shown below:
Port L
Config.
Port L
Data
Port L
Setup
0
0
Hi-Z Input (TRI-STATE)
0
1
Input with Weak Pull-up
1
0
Push-pull Zero Output
1
1
Push-pull One Output
Three data memory address locations are allocated for this
port, one each for data register [00D0], configuration regis
ter [00D1] and the input pins [00D2],
Port L has the following alternate features:
LO MIWU or CMPOUT
L1 MIWU or CMPIN-
L2 MIWU or CMPIN +
L3 MIWU
L4 MIWU (high sink current capability)
L5 MIWU (high sink current capability)
L6 MIWU (high sink current capability)
L7 MIWU or MODOUT (high sink current capability)
The selection of alternate Port L functions is done through
registers WKEN [00C9] to enable MIWU and CNTRL2
[OOCC] to enable comparator and modulator.
All eight L-pins have Schmitt Triggers on their inputs.
PORT G
is an 8-bit port with 6 I/O pins (G0-G5) and 2 input
pins (G6, G7).
All eight G-pins have Schmitt Triggers on the inputs.
There are two registers associated with the G port: a data
register and a configuration register. Therefore each G port
bit can be individually configured under software control as
shown below:
PortG
Config.
PortG
Data
PortG
Setup
o
n
UI "7 1 nrv (TDI CTA *rr^
• ii 4—
it i|*/m
yl
i
■ /-\ i
l
_f
0
1
Input with Weak Pull-up
1
0
Push-pull Zero Output
1
1
Push-pull One Output
Three data memory address locations are allocated for this
port, one for data register [00D3], one for configuration reg
ister [00D5] and one for the input pins [OOD6]. Since G6
and G7 are Hi-Z input only pins, any attempt by the user to
configure them as outputs by writing a one to the configura
tion register will be disregarded. Reading the G6 and G7
configuration bits will return zeros. Note that the device will
be placed in the Halt mode by writing a “ 1” to the G7 data
bit.
Six pins of Port G have alternate features:
GO INTR (an external interrupt)
G3 TIO (timer/counter input/output)
G4 SO (MICROWIRE serial data output)
G5 SK (MICROWIRE clock I/O)
G6 SI (MICROWIRE serial data input)
G7 CKO crystal oscillator output (selected by mask option)
or HALT restart input/general purpose input (if clock
option is R/C or external clock)
1-55
COP820CJ
/COP
822
CJ/C
OP8
23C
J
