Current Drain
The total current drain of the chip depends on:
1. Oscillator operating mode - !1
2. Internal switching current - 12
3. Internal leakage current - I3
4. Output source current - 14
5. DC current caused by external input not at V<x or
G N D -I5
6. DC current caused by the comparator (if comparator is
enabled) - 16
7. DC current caused by the Brown Out - 17
Thus the total current drain is given as
It = 11 + I2 + I3 + I4 + I5 + I6 + I7
To reduce the total current drain, each of the above compo
nents must be minimum. Operating with a crystal network
will draw more current than an external square-wave. The
R/C-mode will draw the most. Switching current, governed
by the equation below, can be reduced by lowering voltage
and frequency. Leakage current can be reduced by lowering
voltage and temperature. The other two items can be re
duced by carefully designing the end-user’s system.
The following formula may be used to compute total current
drain when operating the controller in different modes.
I2 = C
X
V
X
f
where: C = equivalent capacitance of the chip
V = operating voltage
f = CKI frequency
Halt Mode
The device is a fully static device. The device enters the
HALT mode by writing a one to the G7 bit of the G data
register. Once in the HALT mode, the internal circuitry does
not receive any clock signal and is therefore frozen in the
exact state it was in when halted. In this mode the chip will
only draw leakage current (output current and DC current
due to the Brown Out circuit if Brown Out is enabled).
The device supports four different methods of exiting the
HALT mode. The first method is with a low to high transition
on the CKO (G7) pin. This method precludes the use of the
crystal clock configuration (since CKO is a dedicated out
put). It may be used either with an RC clock configuration or
an external clock configuration. The second method of exit
ing the HALT mode is with the multi-input Wakeup feature
on the L port. The third method of exiting the HALT mode is
by pulling the RESET input low. The fourth method is with
the operating voltage going below Brown Out voltage (if
Brown Out is enabled by mask option).
Functional Description
(Continued)
If the two pin crystal/resonator oscillator is being used and
Multi-Input Wakeup or Brown Out causes the device to exit
the HALT mode, the WAKEUP signal does not allow the
chip to start running immediately since crystal oscillators
have a delayed start up time to reach full amplitude and
freuqency stability. The WATCHDOG timer (consisting of an
8-bit prescaler followed by an 8-bit counter) is used to gen
erate a fixed delay of 256tc to ensure that the oscillator has
indeed stabilized before allowing instruction execution. In
this case, upon detecting a valid WAKEUP signal only the
oscillator circuitry is enabled. The WATCHDOG Counter and
Prescaler are each loaded with a value of FF Hex. The
WATCHDOG prescaler is clocked with the tc instruction cy
cle. (The tc clock is derived by dividing the oscillator clock
down by a factor of 10). The Schmitt trigger following the
CKI inverter on the chip ensures that the WATCHDOG timer
is clocked only when the oscillator has a sufficiently large
amplitude to meet the Schmitt trigger specs. This Schmitt
trigger is not part of the oscillator closed loop. The start-up
timeout from the WATCHDOG timer enables the clock sig
nals to be routed to the rest of the chip. The delay is not
activated when the device comes out of HALT mode
through RESET pin. Also, if the clock option is either RC or
External clock, the delay is not used, but the WATCHDOG
Prescaler/-Counter contents are changed. The Develop
ment System will not emulate the 256tc delay.
The RESET pin or Brown Out will cause the device to reset
and start executing from address X’0000. A low to high tran
sition on the G7 pin (if single pin oscillator is used) or Multi-
Input Wakeup will cause the device to start executing from
the address following the HALT instruction.
When RESET pin is used to exit the device from the HALT
mode and the two pin crystal/resonator (CKI/CKO) clock
option is selected, the contents of the Accumulator and the
Timer T1 are undetermined following the reset. All other
information except the WATCHDOG Prescaler/Counter
contents is retained until continuing. If the device comes out
of the HALT mode through Brown Out reset, the contents of
data registers and RAM are unknown following the reset. All
information except the WATCHDOG Prescaler/Counter
contents is retained if the device exits the HALT mode
through G7 pin or Multi-Input Wakeup.
G7 is the HALT-restart pin, but it can still be used as an
input. If the device is not halted, G7 can be used as a gener
al purpose input.
If the Brown Out Enable mask option is selected, the Brown
Out circuit remains active during the HALT mode causing
additional current to be drawn.
Note:
To allow clock resynchronization, it is necessary to program two
NOP’s immediately after the device comes out of the HALT mode.
The user must program two NOP’s following the “ enter HALT mode"
(set G7 data bit) instruction.
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