F u n c tio n a l D e s c rip tio n
(Continued)
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by
the Master will be shifted properly. After eight clock pulses
the BUSY flag will be cleared and the sequence may be
repeated.
TABLE IV
G4
Conflg.
Bit
G5
Conflg.
Bit
G4
Fun.
G5
Fun.
G6
Fun.
Operation
1
1
SO
Int. SK
SI
MICROWIRE Master
0
1
TRI-STATE
Int. SK
SI
MICROWIRE Master
1
0
SO
Ext. SK
SI
MICROWIRE Slave
0
0
TRI-STATE
Ext. SK
SI
MICROWIRE Slave
MODE 1. TIMER WITH AUTO-LOAD REGISTER
In this mode of operation, the timer T1 counts down at the
instruction cycle rate. Upon underflow the value in the regis
ter R1 gets automatically reloaded into the timer which con
tinues to count down. The timer underflow can be pro
grammed to interrupt the microcontroller. A bit in the control
register CNTRL enables the TIO (G3) pin to toggle upon
timer underflows. This allows the generation of square-wave
outputs or pulse width modulated outputs under software
control
(Figure 8).
MODE 2. EXTERNAL COUNTER
In this mode, the timer T1 becomes a 16-bit external event
counter. The counter counts down upon an edge on the TIO
pin. Control bits in the register CNTRL program the counter
to decrement either on a positive edge or on a negative
edge. Upon underflow the contents of the register R1 are
automatically copied into the counter. The underflow can
also be programmed to generate an interrupt
(Figure 9).
T im e r /C o u n te r
The device has a powerful 16-bit timer with an associated
16-bit register enabling it to perform extensive timer func
tions. The timer T1 and its register R1 are each organized
as two 8-bit read/write registers. Control bits in the register
CNTRL allow the timer to be started and stopped under
software control. The timer-register pair can be operated in
one of three possible modes. Table V details various timer
operating modes and their requisite control settings.
no
'
o u t p u t
TL/DD/11208-24
FIGURE 8. Timer/Counter Auto
Reload Mode Block Diagram
TABLE V. Timer Operating Modes
CNTRL
Bits
7 6 5
Operation Mode
T Interrupt
Timer
Counts
On
0 0 0
External Counter w/Auto-Load Reg.
Timer Underflow
TIO Pos. Edge
001
External Counter w/Auto-Load Reg.
Timer Underflow
TIO Neg. Edge
0 1 0
Not Allowed
Not Allowed
Not Allowed
0 1 1
Not Allowed
Not Allowed
Not Allowed
1 0 0
Timer w/Auto-Load Reg.
Timer Underflow
tc
1 0 1
Timer w/Auto-Load Reg./Toggle TIO Out
Timer Underflow
1 1 0
Timer w/Capture Register
TIO Pos. Edge
111
Timer w/Capture Register
TIO Neg. Edge
INTERNAL DATA BUS
TIMER
UNDERFLOW
INTERRUPT
1 6 -B IT AUTO-RELOAD REGISTER
EXT
CLK
E h U
T1
1 6 -B IT TIMER/COUNTER
EDGE SELECTOR
LOGIC
FIGURE 9. Timer in External Event Counter Mode
TL/DD/11208-29
1-61
COP820CJ
/COP
822
CJ/C
OP8
23C
J
