M u lti-In p u t W a k e u p
(Continued)
INTERNAL DATA BUS
TL/DD/11208-21
FIGURE 16. Multi-Input Wakeup Logic
INTERRUPTS
The device has a sophisticated interrupt structure to allow
easy interface to the real world. There are three possible
interrupt sources, as shown below.
A maskable interrupt on external GO input (positive or nega
tive edge sensitive under software control)
A maskable interrupt on timer carry or timer capture
A non-maskable software/error interrupt on opcode zero
INTERRUPTCONTROL
The GIE (global interrupt enable) bit enables the interrupt
function. This is used in conjunction with ENI and ENTI to
select one or both of the interrupt sources. This bit is reset
when interrupt is acknowledged.
ENI and ENTI bits select external and timer interrupts re
spectively. Thus the user can select either or both sources
to interrupt the microcontroller when GIE is enabled.
IEDG selects the external interrupt edge (0 = rising edge,
1 = falling edge). The user can get an interrupt on both
rising and falling edges by toggling the state of IEDG bit
after each interrupt.
IPND and TPND bits signal which interrupt is pending. After
an interrupt is acknowledged, the user can check these two
bits to determine which interrupt is pending. This permits the
interrupts to be prioritized under software. The pending flags
have to be cleared by the user. Setting the GIE bit high
inside the interrupt subroutine allows nested interrupts.
The software interrupt does not reset the GIE bit. This
means that the controller can be interrupted by other inter
rupt sources while servicing the software interrupt.
INTERRUPT PROCESSING
The interrupt, once acknowledged, pushes the program
counter (PC) onto the stack and the stack pointer (SP) is
decremented twice. The Global Interrupt Enable (GIE) bit is
reset to disable further interrupts. The microcontroller then
vectors to the address 00FFH and resumes execution from
that address. This process takes 7 cycles to complete. At
the end of the interrupt subroutine, any of the following
three instructions return the processor back to the main pro
gram: RET, RETSK or RETI. Either one of the three instruc
tions will pop the stack into the program counter (PC). The
stack pointer is then incremented twice. The RETI instruc
tion additionally sets the GIE bit to re-enable further inter
rupts.
Any of the three instructions can be used to return from a
hardware interrupt subroutine. The RETSK instruction
should be used when returning from a software interrupt
subroutine to avoid entering an infinite loop.
DETECTION OF ILLEGAL CONDITIONS
The device incorporates a hardware mechanism that allows
it to detect illegal conditions which may occur from coding
errors, noise, and “ brown out” voltage drop situations. Spe
cifically, it detects cases of executing out of undefined ROM
area and unbalanced tack situations.
Reading an undefined ROM location returns 00 (hexadeci
mal) as its contents. The opcode for a software interrupt is
also “ CO” . Thus a program accessing undefined RGivi wiii
cause a software interrupt.
Reading an undefined RAM location returns an FF (hexade
cimal). The subroutine stack on the device grows down for
each subroutine call. By initializing the stack pointer to the
top of RAM, the first unbalanced return instruction will cause
the stack pointer to address undefined RAM. As a result the
program will attempt to execute from FFFF (hexadecimal),
which is an undefined ROM location and will trigger a soft
ware interrupt.
TO
INTERRUPT
LOGIC
FIGURE 17. Interrupt Block Diagram
TL/DD/11208-27
1-67
COP8
20C
J/CO
P8
22C
J/CO
P82
3CJ
