COP8
20C
J/CO
P8
22C
J/CO
P82
3CJ
Functional Description
(Continued)
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous bidirectional
communications interface. The MICROWIRE/PLUS capabil
ity enables the device to interface with any of National
Semiconductor’s MICROWIRE peripherals (i.e. A/D con
verters, display drivers, EEPROMS, etc.) and with other mi
crocontrollers which support the MICROWIRE/PLUS inter
face. It consists of an 8-bit serial shift register (SIO) with
serial data input (SI), serial data output (SO) and serial shift
clock (SK).
Figure 6
shows the block diagram of the MICRO
WIRE/PLUS interface.
T L /D D /1 1 2 0 8 -8
FIGURE 6. MICROWIRE/PLUS Block Diagram
The shift clock can be selected from either an internal
source or an external source. Operating the MICROWIRE/
PLUS interface with the internal clock source is called the
Master mode of operation. Operating the MICROWIRE/
PLUS interface with an external shift clock is called the
Slave mode of operation. ,
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. The SK
clock rate is selected by the two bits, SLO and SL1, in the
CNTRL register. Table III details the different clock rates
that may be selected.
TABLE III
SL1
SLO
SK Cycle Time
0
0
2tc
0
1
4tc
1
X
8tc
where,
tc is the instruction cycle time.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the MI
CROWIRE/PLUS arrangement to start shifting the data. It
gets reset when eight data bits have been shifted. The user
may reset the BUSY bit by software to allow less than 8 bits
to shift. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave.
Figure 7
shows how
two device microcontrollers and several peripherals may be
interconnected using the MICROWIRE/PLUS arrangement.
Master MICROWIRE/PLUS Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally by the device. The
MICROWIRE/PLUS Master always initiates all data ex
changes
(Figure 7).
The MSEL bit in the CNTRL register
must be set to enable the SO and SK functions on the G
Port. The SO and SK pins must also be selected as outputs
by setting appropriate bits in the Port G configuration regis
ter. Table IV summarizes the bit settings required for Master
mode of operation.
SLAVE MICROWIRE/PLUS OPERATION
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
on the G Port. The SK pin must be selected as an input and
the SO pin selected as an output pin by appropriately setting
up the Port G configuration register. Table IV summarizes
the settings required to enter the Slave mode of operation.
T L /D D /1 1 2 0 8 -2 3
FIGURE 7. MICROWIRE/PLUS Application
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