Chapter 2
NI 5450 Overview
NI PXIe-5450 User Manual
2-38
ni.com
The following figure shows the NI 5450 Reference Clock Source path.
To begin the PLL, the phase comparator compares the selected Reference
clock to the 400 MHz clock of the Sample clock timebase. Next, a control
voltage proportional to the phase difference between the two clocks is
developed and used to tune the Sample clock timebase into alignment with
the Reference clock. Finally, the Sample clock timebase output is routed
back to the phase comparator, and the loop is closed.
Note
When the Reference Clock Source property or the
NIFGEN_ATTR_REFERENCE_CLOCK_SOURCE
attribute is set to “None”; the internal
calibration DAC generates the calibration voltage, and the PLL circuit is not used.
Reference Clock Sources
The NI 5450 can phase-lock its Sample clock timebase to an external signal
that is present on the CLK IN front panel connector. PXI devices can also
phase–lock to a 10 MHz Reference clock signal provided by the PXI bus
(PXI_CLK10).
Note
Refer to the device specifications for information about available signal levels on the
CLK IN front panel connector.
PXI_CLK10
CLK IN
High
Resolution
Oscillator
PLL
CLK OUT
(None)
Divide/M
Sample Clock
Timebase/M
PLL* W
with Phase
Adjust
Divide/N
Sample
Clock
Timebase
Channel
Delay
Channel
Delay
CH 0
Sample Clock
CH 1
Sample Clock
Divide/K
Reference Clock
External Sample Clock
External Sample Clock Timebase
