Chapter 2
NI 5450 Overview
©
National Instruments Corporation
2-17
NI PXIe-5450 User Manual
Digital Gain
Digital gain multiplies waveform data by a factor you specify in the Digital
Gain property or the
NIFGEN_ATTR_DIGITAL_GAIN
attribute before
converting the data to an analog signal in the DAC. Digital gain can be
changed during generation without the glitches caused by relay switching
that are common when changing analog gains. However, the output
resolution of the DAC is a function of digital gain, meaning that only
analog gain makes full use of the resolution of the DAC.
Flatness Correction
The NI 5450 can use flatness correction to ensure a consistent power level
when generating arbitrary waveforms at any frequency. Flatness correction
is disabled by default in NI-FGEN. You can enable or disable flatness
correction by calling the Flatness Correction Enabled property or the
NIFGEN_ATTR_FLATNESS_CORRECTION_ENABLED
attribute.
During external calibration, the frequency response of the Analog path in
its different configurations is measured using the niFgen Initialize Flatness
Calibration VI or the
niFgen_InitializeFlatnessCalibration
function and the niFgen Cal Adjust Flatness VI or the
niFgen_CalAdjustFlatness
function.
During generation, these measured values are used to compensate for any
attenuation at the requested sample rate. The compensation is applied by a
flatness-correcting FIR filter. This FIR filter applies attenuation to higher
power frequencies so that they become equal to the attenuated frequencies.
As a result, the maximum output voltage is 1.0 V
pk-pk
into a 50
Ω
load.
Filtering Effects
The delay from the time at which the device receives a trigger to the time
at which the analog output signal is generated increases if the digital and/or
analog filters in the Analog Output path are enabled. In the case of digital
filtering, delay also increases with increase in interpolation. Enabling the
onboard signal processing block can also introduce delay.
Note
The digital filter for the signal generator is inside the FPGA, before the Analog
Output path.
