Chapter 2
NI 5450 Overview
©
National Instruments Corporation
2-87
NI PXIe-5450 User Manual
Sample Clock
—The clock signal that tells the DAC when to convert the
digital waveform values to an analog voltage. The Sample clock frequency
is referred to as the Sample clock rate; the rate at which the digital
waveforms from device memory are generated. The Sample clock is also
known as update clock.
Note
The Sample clock can be exported directly, or it can first be divided down by an
integer. This configuration provides a variable frequency signal related to the waveform
sample rate to synchronize other devices to the generation. NI does not recommend
exporting clocks greater than 20 MHz over PXI_TRIG<0..6>. If you export the
divided-down Sample clock to another device to synchronize sampling, you can also use
the Sample clock as the Start trigger for the signal generator. Using the divided-down
Sample clock as the Start trigger begins signal generation at the same place each time
relative to the divided-down Sample clock. This technique is more useful as the divisor
becomes larger and, while an improvement over using an immediate Start trigger, there
remains an uncertainty of one Sample clock.
Sample Clock Timebase
—The 200-400 MHz clock signal from which the
internal Sample clock is derived. The Sample clock timebase is also known
as the board clock.
Note
When the Sample clock timebase (board clock) is exported over PXI_TRIG<0..6>
or the PFI 0 and PFI 1 connectors, it is always divided-down first. The default divide-down
value is 2. Valid divide-down values range from 2 to 4,194,304. If you export the Sample
clock timebase to another device to synchronize sampling, you can also use the Sample
Destination
PXI_TRIG<0..6>
PFI 0 and PFI 1
Connectors
CLK OUT
Exported
Clocks,
Triggers, and
Events
Sample Clock
Yes (when /K
with K
≥
2)
Yes (when /K
with K
≥
2)
Yes
Sample Clock
Timebase
Yes (when /M
with M
≥
2)
Yes (when /M
with M
≥
2)
Yes
PLL Reference
Source
Yes
Yes
Yes
Out Start
trigger
Yes
Yes
No
Marker Event
Yes
Yes
No
