Chapter 2
NI 5450 Overview
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National Instruments Corporation
2-43
NI PXIe-5450 User Manual
CLK OUT connector, or the PXI_Trig<0..6> lines. Refer to the Exported
Sample Clock Divisor property or the
NIFGEN_ATTR_EXPORTED_SAMPLE_CLOCK_DIVISOR
attribute for more
information about configuring the Sample clock divisor.
Sample Clock Timebase
The Sample clock timebase can be routed to the CLK OUT front panel
SMA connector.
Additionally, the exported clock can be divided down by an integer value
before being exported to the PFI <0..1> connectors, the CLK OUT
connector, or the PXI_Trig<0..6> lines. You can configure the Sample
clock divisor by calling the Exported Sample Clock Timebase Divisor
property or the
NIFGEN_ATTR_EXPORTED_SAMPLE_CLOCK_TIMEBASE_DIVISOR
attribute.
Reference Clock
The Reference clock is the actual clock that is configured for the signal
generator phase-locked loop circuit to use as a reference. You configure a
Reference clock as a PLL Reference clock source for the signal to be
available for exporting. The Reference clock can be routed to the
PFI <0..1> front panel SMB connectors, the CLK OUT front panel SMA
connector, or the PXI_Trig<0..6> lines on the PXI trigger bus.
Note
NI-FGEN allows values for Reference clock frequency on the NI 5450 from
1 to 100 MHz in 1 MHz increments, 102 to 200 MHz in 2 MHz increments, and 204 to
400 MHz in 4 MHz increments.
Destination Options
The following sections define the destinations for exported clocks.
PFI <0..1>
—The Sample clock (when K
≥
2), the Sample clock timebase
(when M
≥
2), and the Reference clock can be exported to the PFI 0 and
PFI 1 SMB connectors on the front panel to synchronize external devices.
You must configure the device to export the desired clock to the PFI SMB
connectors.
CLK OUT
—The Sample clock, the Sample clock timebase, and the
Reference clock can be exported to the CLK OUT SMA connectors on the
front panel to synchronize external devices. You must configure the device
to export the desired clock to the CLK OUT SMA connector.
