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Chapter 3
Hardware Overview
PCI/PXI-1408 and NI-IMAQ for Win95/NT
3-4
©
National Instruments Corporation
PCLK, HSYNC, VSYNC Mux
The acquisition control circuitry selects the clock and synchronization
signals through the pixel clock (PCLK), horizontal synchronization
(HSYNC), and vertical synchronization (VSYNC) multiplexer. The
onboard genlock and synchronization circuitry can generate clock and
synchronization signals or the signals can be received from the I/O
connector.
RTSI Bus
The seven trigger lines on the RTSI bus provide a flexible
interconnection scheme between multiple 1408 devices as well as
between any National Instruments DAQ devices and the 1408 device.
Trigger Control and Mapping Circuitry
The trigger control and mapping circuitry routes, monitors, and drives
the external and RTSI bus trigger lines. You can configure each of these
lines to start or stop acquisition on a rising or falling edge. In addition,
you can drive each line asserted or unasserted, similar to a digital I/O
line. You can also map onboard status values (HSYNC, VSYNC,
ACQUISITION_IN_PROGRESS, and ACQUISITION_DONE) to
the lines.
Acquisition and Region-of-Interest Control
The acquisition and region-of-interest control circuitry monitors the
incoming video signal and routes the active pixels to the FIFO buffers.
The 1408 device can digitize an entire frame and perform pixel and line
scaling and region-of-interest acquisition. Pixel and line scaling lets
certain multiples (2, 4, or 8) of pixels and lines to be transferred to the
PCI bus. In region-of-interest acquisition, you select an area in the
acquisition window to transfer to the PCI bus.
FIFO Buffer
The 1408 device uses a 4 KB FIFO buffer for temporary storage of the
image being transferred to the PCI system memory or display memory.
The buffer stores six full video lines during image acquisition.