FPGA
MEN Mikro Elektronik GmbH
92
20A014-00 E2 – 2007-08-16
3.3
Standard Factory FPGA Configuration
3.3.1
IP Cores
The factory FPGA configuration for standard boards comprises the following FPGA
IP cores:
• Main bus interface
• 16Z070_IDEDISK – IDE controller for NAND Flash
• 16Z043_SDRAM – Additional SDRAM controller
• 16Z023_IDE_NHS – IDE controller, non-hot-swap
• 16Z025_UART – UART controller (controls COM10)
• 16Z034_GPIO – GPIO controller (5 IP cores)
This configuration matches the pin assignment given in this manual for the J2 I/O
connector.
3.3.2
FPGA Configuration Table
The resulting configuration table of the standard FPGA is as follows:
Note: 16Z070_IDEDISK consists of three cores:
- 16Z053_IDEATA
- 16Z068_IDETGT (not implemented yet)
- 16Z063_NANDRAW
Table 33.
FPGA – Factory standard configuration table for A14C
IP Core
Device ID
Revision
IRQ
BAR
Offset
16Z054_SYSTEM
23
0
0
0
0
16Z023_IDE_NHS
29
6
1
0
100
16Z034_GPIO
19
1
2
0
200
16Z034_GPIO
19
1
2
0
300
16Z034_GPIO
19
1
2
0
400
16Z034_GPIO
19
1
2
0
500
16Z034_GPIO
19
1
2
0
600
16Z025_UART
7
5
3
0
700
16Z043_SDRAM
21
8
4
1
0
16Z053_IDEATA
22
1
5
2
0
16Z068_IDETGT
31
2
6
3
0
16Z063_NANDRAW
18
3
6
3
600
Magic Word
Variant
Revision
CDEF
A
8
All values are given in
hexadecimal notation.
