Functional Description
MEN Mikro Elektronik GmbH
62
20A014-00 E2 – 2007-08-16
2.16.8
VMEbus Slave Interface
The slave interface consists of 1 MB dual-ported high-speed SRAM. Block transfer
(BLT) is performed with a transfer rate of up to 10 MB/s. RMW cycles are
supported by the slave interface to the SRAM. During an RMW cycle to the SRAM,
a PCI access to the SRAM is blocked.
The A16, A24 and A32 base addresses are defined in the Slave Control Registers.
On simultaneous access by a VMEbus master and the local CPU the VMEbus
master has the highest priority.
The Slave Base Address must be aligned to the chosen size of the window.
SLV24 – Slave Control Register A24 (
0x0014
) (read/write)
SLV16 – Slave Control Register A16 (
0x0030
) (read/write)
15..12
11..8
SLMASK24[19:16]
SLBASE24[19:16]
7..5
4
3..0
SLEN24
SLBASE24[23:20]
SLMASK24
Slave Base Address Mask Bits. The size of the A24 Slave window can
be set to:
0000 =
1000 =
1100 =
1110 =
1111 =
1 MB
512 KB
256 KB
128 KB
64 KB
Default: 0000
SLEN24
0 =
1 =
Slave Unit disabled (default)
Slave Unit enabled
SLBASE24
Slave's Base Address. Specifies the lowest address in the VME address
range that will be decoded. Since only A[23:20] are monitored, the
smallest possible address space is 64 KB.
Default: 00000000
7..5
4
3..0
SLEN16
SLBASE16
SLEN16
0 =
1 =
Slave Unit disabled (default)
Slave Unit enabled
SLBASE16
Slave's Base Address. Specifies the lowest address in the VME address
range that will be decoded. Since only A[15:12] are monitored, the
smallest possible address space is 4 KB.
Default: 0000
