Technical Data
MEN Mikro Elektronik GmbH
4
20A014-00 E2 – 2007-08-16
• One LVTTL UART (COM10)
- FPGA-controlled
- Accessible via rear I/O
- Data rates up to 115.2kbits/s
- 60-byte transmit/receive buffers
- Handshake lines: CTS, RTS; DCD, DSR, DTR; RI
• Quad UART (COM20..COM23)
- Physical interface using SA-Adapters™ via 10-pin ribbon cable on I/O con-
nector
- RS232..RS485, isolated or not: for free use in system (e. g. cable to front)
- Data rates up to 115.2kbits/s
- 128-byte transmit/receive buffer
- Handshake lines: CTS, RTS; DCD, DSR, DTR; RI
• GPIO
- 39 GPIO lines
- FPGA-controlled
- Accessible via rear I/O
Front Connections
• Three Ethernet (RJ45)
• COM1 (RJ45)
• COM20..COM23 (optional, instead of PMC modules, or in second front-panel
slot)
• PMC 0 and 1
Rear I/O
• COM10
• GPIO
• Mezzanine rear I/O: PMC 0
FPGA
• Standard factory FPGA configuration:
- Main bus interface
- 16Z070_IDEDISK - IDE controller for NAND Flash
- 16Z043_SDRAM - Additional SDRAM controller (16MB)
- 16Z023_IDENHS - IDE controller (PIO mode 0; non-hot-swap)
- 16Z025_UART - UART controller (controls COM10)
- 16Z034_GPIO - GPIO controller (40 lines, 5 IP cores)
• The FPGA offers the possibility to add customized I/O functionality. See
FPGA
.
Mezzanine Slots
• Two PMC slots
- Compliant with PMC standard IEEE 1386.1
- Up to 64-bit/64-MHz, 3.3V V(I/O)
- PMC I/O module (PIM) support through J4
