FPGA
MEN Mikro Elektronik GmbH
85
20A014-00 E2 – 2007-08-16
3.2.2
Address Organization
3.2.2.1
Address Map
Table 32.
FPGA – Address map
Address
D15..D0
0x0000
Identification Word
(IW) (r)
0x0004
Magic Word
(MW) (r)
0x0008
Configuration Table
(CT) (r)
0x0080
Interrupt Request Register
(IRQR) (r)
0x0088
Reset Cause Register
(RCR) (r)
0x008C
Watchdog Timer Register
(WDTR) (r/w)
0x0090
Watchdog Value Register
(WDVR) (r/w)
0x0094
System Unit Control Register
(SUCR) (r/w)
0x0098
System Unit Interrupt Request Register
(SUIRQR) (r/w)
0x009C
General Purpose Memory Register
(GPMR) (r/w)
0x00A4..0x00FF
Reserved
0x0100..0x1FFF
FPGA IP cores (see detailed address map in the respective
IP core user manual)
