MEN Mikro Elektronik A14C - 6U VME64 MPC8540, User Manual

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Functional Description
MEN Mikro Elektronik GmbH 54
20A014-00 E2 – 2007-08-16
2.16.2 Runtime Registers
The registers are accessible both from the PCI and the VMEbus side.
From the PCI-bus side the address is the value of BAR 0 (e.g.
0x 8800 0000
) plus
an offset (
0x 0180 0000
) plus the register address (e.g.
0x 0008
for ISTAT).
From the VMEbus side, the registers are accessible in A16 mode only. (E.g. slave
base address A16 =
0x00001000
, plus register address).
Table 17. VMEbus runtime registers
Address D31..D0
0x 0000
INTR – VME Interrupt Control Register (r/w)
0x 0004
INTID – VME Interrupt STATUS/ID Register (r/w)
0x 0008
ISTAT – Interrupt Status Register (r)
0x 000C
IMASK – Interrupt Mask Register (r/w)
0x 0010
MSTR – Master Control Register (r/w)
0x 0014
SLV24 – Slave Control Register A24 (r/w)
0x 0018
SYSCTL – System Controller Register (r/w)
0x 001C
LONGADD – Upper 3 Address Bits for A32 (r/w)
0x 0020
MAIL_IRQE – Mailbox Interrupt Enable Register (r/w)
0x 0024
MAIL_IRQ – Mailbox Interrupt Request Register (r/w)
0x 0028
PCI_OFFSET – PCI Offset Address (r/w)
0x 002C
DMASTA – DMA Status Register (r/w)
0x 0030
SLV16 – Slave Control Register A16 (r/w)
0x 0034
SLV32 – Slave Control Register A32 (r/w)
0x 0038
LOCSTA_0 – Location Status Register (r/w)
0x 003C
LOCSTA_1 – Location Status Register (r/w)
0x 0040
LOCADDR_0 – Location Monitor Address Register (r/w)
0x 0044
LOCADDR_1 – Location Monitor Address Register (r/w)
0x 0048
SLV24_PCI – A24 Slave Base Address for PCI (r/w)
0x 004C
SLV32_PCI – A32 Slave Base Address for PCI (r/w)
0x FF800
MAILBOX_0 – Mailbox Data Register (r/w)
0x FF804
MAILBOX_1 – Mailbox Data Register (r/w)
0x FF808
MAILBOX_2 – Mailbox Data Register (r/w)
0x FF80C
MAILBOX_3 – Mailbox Data Register (r/w)
0x FF900..FF90C
DMA_BD#1 – DMA Buffer Descriptor (r/w)
0x FF910..FF91C
DMA_BD#2 – DMA Buffer Descriptor (r/w)
.. 0x 0FF0..0FFC
Further Buffer Descriptors