Functional Description
MEN Mikro Elektronik GmbH
71
20A014-00 E2 – 2007-08-16
2.16.13
Mailbox
You can use the mailbox feature to send messages without using the slow interrupt
daisy chain. Writing and/or reading one of the data registers of the mailbox from the
VMEbus side generates a local interrupt.
MAIL_IRQE – Mailbox Interrupt Enable Register (
0x0020
) (read/write)
MAIL_IRQ – Mailbox Interrupt Request Register (
0x0024
) (read/write)
MAILBOX_0..MAILBOX_3 – Mailbox Data Register (
0xFF800
,
0xFF804
,
0xFF808
,
0xFF80C
) (read/write)
Writing or reading this register results in an interrupt in the
MAIL_IRQ – Mailbox
Interrupt Request Register (
0x0024
) (read/write)
, if the interrupt is enabled in the
MAIL_IRQE – Mailbox Interrupt Enable Register (
0x0020
) (read/write)
.
This data register can be used to transmit a status or ID.
7
6
5
4
3
2
1
0
IEVW3
IEVR3
IEVW2
IEVR2
IEVW1
IEVR1
IEVW0
IEVR0
IEVWx
VMEbus write access to mailbox register
x
generates an interrupter request
on the PCI-bus when this bit is set.
Default:
0x0
(interrupt disabled)
This bit can be set and reset from both sides (PCI side and VMEbus side).
If both sides access this bit, the VMEbus side wins.
IEVRx
VMEbus read access to mailbox register
x
generates an interrupter request
on the PCI-bus side when this bit is set.
Default:
0x0
(interrupt disabled)
This bit can be set and reset from both sides (PCI side and VMEbus side).
If both sides access this bit, the VMEbus side wins.
7
6
5
4
3
2
1
0
IPVW3
IPVR3
IPVW2
IPVR2
IPVW1
IPVR1
IPVW0
IPVR0
IPVWx
Interrupter pending on the PCI bus because of VMEbus write access to
mailbox register
x
. Cleared by writing 1.
Note: Any IRQ bit will only be set if the corresponding enable bit is set!
IPVRx
Interrupter pending on the PCI bus because of VMEbus read access to
mailbox register
x
. Cleared by writing 1.
Default:
0x0
(no interrupt pending)
This bit can be cleared from both sides.
31..0
Data
