FPGA
MEN Mikro Elektronik GmbH
82
20A014-00 E2 – 2007-08-16
3
FPGA
3.1
General
The FPGA – as a part of the A14C – represents an interface between a user-
selectable configuration of I/O modules (IP cores) and the PCI bus. The PCI core
included in the FPGA can be a PCI target or master. It can be accessed via memory
single/burst read/write cycles.
The Wishbone bus is the uniform interface where IP cores can be connected in
addition to the System Unit to provide the highest possible flexibility for different
configurations of the FPGA.
Each implementation contains a bridge from the PCI bus to the Wishbone bus.
Additionally each implementation contains a system unit for system-specific
functions such as reset/interrupt control or watchdog etc. and the system library. The
presence of the single system unit functions (and system registers) depends on the
necessity in the actual implementation and cannot be described in general.
Figure 8.
FPGA – Block diagram
The FPGA
System Unit
contains a configuration table providing the information
which modules are implemented (device number) in the current configuration.
Furthermore the revision, the instance number (one module can be instantiated more
than one time), the interrupt routing and the base address of the module are stored.
At initialization time, the CPU has to read the configuration table to get the
information of the base addresses of the included modules.
Note that with regard to the FPGA resources such as available logic elements or pins
it is not possible to grant all possible combinations of the FPGA IP cores.
Chapter
3.3 Standard Factory FPGA Configuration on page 92
describes one possible
configuration of the FPGA. Please ask our
sales staff
for other configurations.
Wishbone
Interconnection
FPGA IP Core 1
System Unit
FPGA IP Core 2
...
FPGA IP Core n
...
PCI bus
I/O signals
I/O signals
I/O signals
FPGA
PCI-to-
Wishbone
Bridge
PCI
Master
PCI
Slave
