FPGA
MEN Mikro Elektronik GmbH
89
20A014-00 E2 – 2007-08-16
Watchdog Value Register WDVR (
0x0090
) (read/write)
The WDVR contains the alternating watchdog trigger value. The watchdog has to be
triggered by the CPU with write operations using the alternating values
0xAAAA
and
0x5555
.
Reset value:
0x0000
Reset Controller Control Register RCCR (
0x0094
) (read/write)
The RCCR enables or disables the interrupt request from the reset controller by
setting bit
RCIREN
to 1 or 0 and offers the possibility to reset the A14C through a
CPU register access (bit
SW_RST
). Writing 1 to bit
SW_RST
forces a reset of the
complete module including the FPGA. Bit
HB
is used to trigger a heartbeat LED.
Reset value:
0x0000
15..0
Watchdog trigger value
15..3
2
1
0
Reserved for future use
HB
SW_RST RCIREN
HB
0 = Heartbeat LED turned on
1 = Heartbeat LED turned off
SW_RST
0 = CPU reset inactive
1 = CPU reset active
RCIREN
0 = Reset controller interrupt request disabled
1 = Reset controller interrupt request enabled
