Technical Data
MEN Mikro Elektronik GmbH
3
20A014-00 E2 – 2007-08-16
Technical Data
CPU
• PowerPC®
- MPC8540 PowerQUICC™ III
- 800MHz (666..833MHz optional)
- e500 PowerPC® core with SPE APU and MMU
- Integrated Northbridge and Southbridge
- High memory bandwidth
Memory
• 2x32KB L1 data and instruction cache, 256KB L2 cache / SRAM integrated in
MPC8540
• Up to 2GB SDRAM system memory
- SO-DIMM slot for SDRAM modules
- DDR2100 with or without ECC
- 133MHz memory bus frequency
• Up to 1GB soldered NAND Flash (and more), FPGA-controlled
• Up to 16MB additional SDRAM, FPGA-controlled, e.g. for video data and
NAND Flash firmware
• 8MB boot Flash
• 32KB non-volatile FRAM
• Serial EEPROM 4kbits for factory settings
Mass Storage
• Parallel IDE (PATA)
- One port for hard-disk drives
- Drive can be connected via ribbon cable or mounted directly on the CPU
board using MEN adapter kit (instead of PMC modules)
- Only one VMEbus slot needed even with hard disk
- PIO mode 0 support
• Up to 1GB soldered ATA NAND Flash (and more), FPGA-controlled
I/O
• Three Ethernet channels
- Two 10/100/1000Base-T Ethernet channels
- One 10/100Base-T Ethernet channel
- Three RJ45 connectors at front panel
- Two on-board LEDs to signal LAN Link and Activity
• One RS232 UART (COM1)
- One RJ45 connector at front panel
- Data rates up to 115.2kbits/s
- 16-byte transmit/receive buffer
- Handshake lines: CTS, RTS
