PWRDOWN
Meaning:
Power-Down the MAX3420E.
Location:
USBCTL.4
Set:
The CPU sets this bit to put the chip into the low power state required by a USP
peripheral in the suspended state.
Clear:
The CPU clears this bit to take the chip out of the low power state and resume
operation.
POR:
PWRDOWN=0
Chip Reset:
No change
Bus Reset:
No change
Pwr Down:
Read-write
Programming Notes:
The power-down operation is triggered by the 0-1 transition of the PWRDOWN bit. Therefore if
the chip wakes up while the bit PWRDOWN=1 (see below for the various wakeup methods), it
will not immediately power down again.
Any wakeup routine should clear the PWRDOWN bit to
ready it for the next 0-1 transition.
The CPU normally puts the MAX3420E into its power-down mode by setting PWRDOWN=1
and HOSCSTEN=1 (page 37). When the CPU sets PWRDOWN=1, the SIE takes the following
actions:
•
Stops the internal 12 MHz oscillator.
•
Monitors the USB DPLUS pin for bus activity.
•
Monitors the SPI port for access to a limited set of registers (e.g. USBCTL).
Once in the low power state (PWRDOWN=1), the chip may wake up in two ways:
1. The CPU clears the PWRDOWN bit.
This starts the internal oscillator, and once stable, the SIE activates the OSCOK IRQ (page 49).
2.
The SIE detects activity on DPLUS and the bit HOSCSTEN=1
.
See page 37 for a description of the special case of a self-powered device that sets
HOSCSTEN=0.
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