MISO bit Signal
page
7 SUSPIRQ
6 URESIRQ
5 SUDAVIRQ
2 OUT1DAVIRQ
1 OUT0DAVIRQ
Figure 4. Full-duplex mode: These USB status bits
are clocked out while the command byte is clocked in.
The SPI Command Byte
In either SPI mode, the first byte clocked into the SPI interface is a command byte that sets the
register address, the direction, and a bit that directly sets the ACKSTAT bit. In all SPI
transactions, in or out, the bit ordering is b7 first, b0 last.
MOSI bit Signal
7 REG4
6 REG3
5 REG2
4 REG1
3 REG0
2 0
1 Direction
(1=Wr,
0=Rd)
0
ACKSTAT (page 1)
Figure 5. The SPI command byte.
An SPI cycle starts with the SPI master driving CS# low, then driving eight SPI clocks whose
rising edges strobe in the data shown in the Figure 5 command byte. REG[4:0] set the register
address, and the direction bit sets the read or write direction for the SPI cycle. ACKSTAT writes
the corresponding bit in the EPSTALLS register. If FDUPSPI=1, the data shown in Figure 4 is
simultaneously clocked out on the MISO pin during these first 8 SCLK clocks.
Following the command byte, the SPI master issues one or more groups of 8-SCLK clocks to
clock byte data into or out of the MAX3420E. As long as CS# remains low, the register address
clocked in with the command remains in effect. This ability to burst bytes is convenient when
reading or writing the endpoint FIFOS. For example, to load 37 bytes into the EP0FIFO, the SPI
master writes the command byte 00000010 which selects R0 (EP0FIFO) for a write operation
(direction bit is 1). Then it writes 37 bytes to the SPI port, and finally drives CS# high to
complete the SPI cycle.
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