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Maxim Integrated MAX3420E Programming Manual Download Page 44

IN0BAVIRQ 

 
 
Meaning:  

Endpoint 0 IN Buffer Available Interrupt Request. 

 
Location: 

EPIRQ.0 

 
Set: 

The SIE sets this bit after receiving an IN token directed to Endpoint 0, sending 
the data in the EP0FIFO (page 10) and receiving the ACK handshake from the 
host. This indicates that the EP0FIFO is again available for loading by the CPU. 

 
Clear: 

The CPU resets this bit by writing a “1” to it, or by writing the byte count register 
EP0BC (page 9). 

 

POR:  

IN0BAVIRQ=1

 

Chip Reset:

 IN0BAVIRQ=1 

 

Bus Reset: 

IN0BAVIRQ=1  

Pwr Down: 

Read-only

 
 
 
 
 
 

 

40

Summary of Contents for MAX3420E

Page 1: ...ore information on the MAX3420E please visit http www maxim ic com max3420e For more information on USB and Maxim s USB products see http www maxim ic com usb The Maxim logo is a registered trademark...

Page 2: ...STLSTAT STLEP3IN STLEP2IN STLEP1OUT STLEP0OUT STLEP0IN RSC R10 CLRTOGS EP3DISAB EP2DISAB EP1DISAB CTGEP3IN CTGEP2IN CTGEP1OUT 0 0 RSC R11 EPIRQ 0 0 SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ...

Page 3: ...e SPI master provides additional bursts of eight SCLK pulses for each byte When the byte transfers are complete the SPI master de asserts SS drives high and the transfer terminates It is possible to t...

Page 4: ...otal of 8 bytes 5 Set SS 1 Registers R5 R20 are control registers If the SPI master repeatedly reads or writes R5 R20 during the same SPI transfer SS low every byte read or write automatically increme...

Page 5: ...ears the SUDAVIRQ bit by writing 1 to it and then reads the eight data bytes from the SUDFIFO into memory The CPU then inspects the eight bytes to determine the nature of the USB request If the reques...

Page 6: ...lears this bit to disable the BUSACT IRQ POR BUSACTIE 0 Chip Reset BUSACTIE 0 Bus Reset BUSACTIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable bits are cleared during a U...

Page 7: ...SACT signal is set when the SIE receives a SYNC field and reset after 32 bit time of a J state or during a USB bus reset The BUSACTIRQ bit is set when the internal BUSACT signal makes a 0 1 transition...

Page 8: ...eset the chip Its effect is identical to driving the RES pin low Clear The CPU clears this bit to take the chip out of reset POR CHIPRES 0 Chip Reset No change Bus Reset No change Pwr Down Read write...

Page 9: ...ends on the setting of the VBGATE bit page 76 If CONNECT 1 and VBGATE 1 internal logic will not connect the pullup resistor unless VBUS is detected to be valid on the VBUS pin If VBGATE 0 the DPLUS pu...

Page 10: ...y clears this bit POR CTGEP1OUT 0 Chip Reset CTGEP1OUT 0 Bus Reset CTGEP1OUT 0 Pwr Down Read only Programming Notes The SIE automatically clears all data toggles during a chip or USB bus reset The CPU...

Page 11: ...y clears this bit POR CTGEP2IN 0 Chip Reset CTGEP2IN 0 Bus Reset CTGEP2IN 0 Pwr Down Read only Programming Notes The SIE automatically clears all data toggles during a chip or USB bus reset The CPU no...

Page 12: ...y clears this bit POR CTGEP3IN 0 Chip Reset CTGEP3IN 0 Bus Reset CTGEP3IN 0 Pwr Down Read only Programming Notes The SIE automatically clears all data toggles during a chip or USB bus reset The CPU no...

Page 13: ...returns a data packet instead of a NAK to the next IN request to the endpoint Read OUT For an OUT transfer the SIE loads the byte count to indicate the number of bytes received in an OUT data transfer...

Page 14: ...T For an OUT transfer the SIE fills the FIFO with USB data received from the host When the OUT transfer is verified to be error free the SIE loads the byte count register page 9 to indicate the number...

Page 15: ...EP0IBN 0 Chip Reset EP0IBN 0 Bus Reset EP0IBN 0 Pwr Down Read write Programming Notes This bit may be polled to discover that the host is asking for IN data which is not yet available from an IN endpo...

Page 16: ...EP1DISAB 0 Chip Reset EP1DISAB 0 Bus Reset EP1DISAB 0 Pwr Down Read only Programming Notes A disabled endpoint does not respond to any traffic A host normally will never send traffic to an endpoint th...

Page 17: ...h performance in many systems See the OUT1DAVIRQ bit discussion page 51 for a description of how the double buffering works for an OUT endpoint The double buffering is invisible to the programmer beca...

Page 18: ...IFO while the CPU reads data from the other This improves bandwidth performance in many systems See the OUT1DAVIRQ bit discussion page 53 for a description of how the double buffering works for an OUT...

Page 19: ...ISAB 0 Chip Reset EP2DISAB 0 Bus Reset EP2DISAB 0 Pwr Down Read only Programming Notes A disabled endpoint does not respond to any traffic A host normally will never send traffic to an endpoint that i...

Page 20: ...t POR EP2INAK 0 Chip Reset EP2INAK 0 Bus Reset EP2INAK 0 Pwr Down Read write Programming Notes This bit may be polled to discover that the host is asking for IN data which is not yet available from an...

Page 21: ...s this register with the number of bytes it has loaded into the EP2INFIFO page 18 This arms the endpoint for the next IN transfer Read The SIE sends the data in this FIFO as the response to an EP2 IN...

Page 22: ...ocation EP2INFIFO 7 0 Write The CPU loads bytes into this FIFO in preparation for sending to the host Read The SIE sends these bytes over USB in response to an IN request to EP2 IN POR EP2INFIFO 0 Chi...

Page 23: ...DISAB 0 Chip Reset EP3DISAB 0 Bus Reset EP3DISAB 0 Pwr Down Read only Programming Notes A disabled endpoint does not respond to any traffic A host normally will never send traffic to an endpoint that...

Page 24: ...t POR EP3INAK 0 Chip Reset EP3INAK 0 Bus Reset EP3INAK 0 Pwr Down Read write Programming Notes This bit may be polled to discover that the host is asking for IN data which is not yet available from an...

Page 25: ...with the number of bytes it has previously loaded into the EP3INFIFO page 22 This arms the endpoint for the next IN transfer Read The SIE sends the data in this FIFO as the response to an EP3 IN host...

Page 26: ...EP3INFIFO 7 0 Write The CPU loads bytes into this FIFO in preparation for sending to the host Read The SIE sends these bytes over USB in response to an IN request to EP3 IN POR EP3INFIFO 0 Chip Reset...

Page 27: ...DUPSPI 0 the MOSI Master Out Slave In pin becomes a bi directional IO pin and the MISO Master In Slave Out pin is tri stated MOSI MISO 8 bit SR SPI Direction FDUPSPI 0 default Figure 2 Half duplex SPI...

Page 28: ...rising edges strobe in the data shown in the Figure 5 command byte REG 4 0 set the register address and the direction bit sets the read or write direction for the SPI cycle ACKSTAT writes the correspo...

Page 29: ...ts the MOSI data to be available before the first positive clock edge can operate in modes 0 0 and 1 1 without alteration This property allows the MAX3420E to operate in mode 0 0 or 1 1 without requir...

Page 30: ...es this register after receiving the ACK handshake at the conclusion of a Set_Address request from the host Clear The SIE clears this register during a chip reset or a USB bus reset POR FNADDR 0 Chip...

Page 31: ...s pin indicates the state of the GPIN0 pin referenced to VL This pin is pulled high with a weak pullup resistor so if nothing is connected to the pin it indicates logic 1 Clear Writing this bit has no...

Page 32: ...s pin indicates the state of the GPIN1 pin referenced to VL This pin is pulled high with a weak pullup resistor so if nothing is connected to the pin it indicates logic 1 Clear Writing this bit has no...

Page 33: ...s pin indicates the state of the GPIN2 pin referenced to VL This pin is pulled high with a weak pullup resistor so if nothing is connected to the pin it indicates logic 1 Clear Writing this bit has no...

Page 34: ...s pin indicates the state of the GPIN3 pin referenced to VL This pin is pulled high with a weak pullup resistor so if nothing is connected to the pin it indicates logic 1 Clear Writing this bit has no...

Page 35: ...bit indicates the state of the output flipflop before the output buffer Therefore if the output pin is driving a large load e g an LED that compromises the logic level the CPU can still read the corr...

Page 36: ...bit indicates the state of the output flipflop before the output buffer Therefore if the output pin is driving a large load e g an LED that compromises the logic level the CPU can still read the corr...

Page 37: ...bit indicates the state of the output flipflop before the output buffer Therefore if the output pin is driving a large load e g an LED that compromises the logic level the CPU can still read the corr...

Page 38: ...bit indicates the state of the output flipflop before the output buffer Therefore if the output pin is driving a large load e g an LED that compromises the logic level the CPU can still read the corr...

Page 39: ...he CPU sets this bit Clear The CPU clears this bit POR GPXA 0 Chip Reset No change Bus Reset No change Pwr Down Read write Programming Notes GPXB GPXA GPX Pin 0 0 OPERATE complement of internal POR 0...

Page 40: ...he CPU sets this bit Clear The CPU clears this bit POR GPXB 0 Chip Reset No change Bus Reset No change Pwr Down Read write Programming Notes GPXB GPXA GPX Pin 0 0 OPERATE complement of internal POR 0...

Page 41: ...ith a special case of item 3 when the MAX3420E is designed into a self powered peripheral Suppose a user plugs a self powered peripheral which is in power down mode into a PC that is turned off The lo...

Page 42: ...of the INT output pin are programmed by the INTLEVEL page 45 and POSINT page 54 bits Clear The CPU clears this bit to disable the INT output pin When IE 0 the state of the INT pin is inactive open for...

Page 43: ...ear The CPU clears this bit to disable the IN0BAV interrupt request POR IN0BAVIE 0 Chip Reset IN0BAVIE 0 Bus Reset IN0BAVIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable...

Page 44: ...point 0 sending the data in the EP0FIFO page 10 and receiving the ACK handshake from the host This indicates that the EP0FIFO is again available for loading by the CPU Clear The CPU resets this bit by...

Page 45: ...ar The CPU clears this bit to disable the IN2BAV interrupt request POR IN2BAVIE 0 Chip Reset IN2BAVIE 0 Bus Reset IN2BAVIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable b...

Page 46: ...ut of one IN FIFO while the CPU loads data into the other This improves bandwidth performance in many systems The IN2BAVIRQ flag logic makes the double buffering invisible to the programmer For exampl...

Page 47: ...ar The CPU clears this bit to disable the IN3BAV interrupt request POR IN3BAVIE 0 Chip Reset IN3BAVIE 0 Bus Reset IN3BAVIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable b...

Page 48: ...rom the host This indicates that the EP3INFIFO is again available for loading by the CPU Clear The CPU clears this bit by writing the byte count register EP3INBC page 21 POR IN3BAVIRQ 1 Chip Reset IN3...

Page 49: ...INTLEVEL 0 Chip Reset No change Bus Reset No change Pwr Down Read write Programming Notes Clear first IRQ second IRQ still active INTLEVEL 1 POSINT X First IRQ Active Second IRQ Active Clear last pen...

Page 50: ...the NOVBUS Interrupt Request POR NOVBUSIE 0 Chip Reset NOVBUSIE 0 Bus Reset NOVBUSIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable bits are cleared during a USB bus reset...

Page 51: ...t threshold Clear The CPU clears this bit by writing a 1 to it POR NOVBUSIRQ 0 Chip Reset NOVBUSIRQ 0 Bus Reset NOVBUSIRQ 0 Pwr Down Read only Programming Notes This IRQ bit provides an easy way for a...

Page 52: ...clears this bit to disable the OSCOK Interrupt Request POR OSCOKIE 0 Chip Reset OSCOKIE 0 Bus Reset OSCOKIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable bits are cleare...

Page 53: ...rnal 12 MHz oscillator is stable and the chip is ready to operate The SIE sets the OSCOKIRQ bit when the OSCOK signal makes a 0 1 transition indicating that the chip is ready to operate Clear The CPU...

Page 54: ...r The CPU clears this bit to disable the OUT0DAV interrupt request POR OUT0DAVIE 0 Chip Reset OUT0DAVIE 0 Bus Reset OUT0DAVIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enabl...

Page 55: ...Set The SIE sets this bit when it has successfully received and ACK d an OUT data packet to EP0 Clear The CPU clears this bit by writing a 1 to it This also arms the endpoint for another transfer POR...

Page 56: ...r The CPU clears this bit to disable the OUT1DAV Interrupt Request POR OUT1DAVIE 0 Chip Reset OUT1DAVIE 0 Bus Reset OUT1DAVIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enabl...

Page 57: ...ering invisible to the programmer For example assume that both buffers are available and therefore OUT1DAVIRQ 0 When an OUT packet arrives OUT1DAVIRQ makes a 0 1 transition to indicate availability of...

Page 58: ...IRQ Active Clear last pending IRQ Single IRQ Clear IRQ 1 2 1 Width determined by clearing the IRQ 2 Fixed at 20 usec INTLEVEL 0 POSINT X INTLEVEL 0 POSINT X Figure 9 INT pin behavior depending on INTL...

Page 59: ...n again Any wakeup routine should clear the PWRDOWN bit to ready it for the next 0 1 transition The CPU normally puts the MAX3420E into its power down mode by setting PWRDOWN 1 and HOSCSTEN 1 page 37...

Page 60: ...The CPU clears this bit to disable the RWUDN interrupt request POR RWUDNIE 0 Chip Reset RWUDNIE 0 Bus Reset RWUDNIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable bits ar...

Page 61: ...The SIE sets this bit at the end of RWU signaling 10 ms of a K state Clear The CPU clears this bit by writing a 1 to it POR RWUDNIRQ 0 Chip Reset RWUDNIRQ 0 Bus Reset RWUDNIRQ 0 Pwr Down Read only Pro...

Page 62: ...ze before initiating the RWU signaling The SPI master sets SIGRWU 1 and waits for the SIE to assert the RWUDNIRQ page 57 to indicate that the signaling interval is over When RWUDNIRQ asserts the SPI m...

Page 63: ...ake to indicate an illegal or unknown request to endpoint 0 Endpoint 0 has three stall bits to account for the status stage and the optional IN and OUT data stages that the transfer may use STLSTAT pa...

Page 64: ...dshake to indicate an illegal or unknown request to endpoint 0 Endpoint 0 has three stall bits to account for the status stage and the optional IN and OUT data stages that the transfer may use STLSTAT...

Page 65: ...handshake for an OUT request directed to endpoint 1 Clear The CPU clears this bit to return EP1 OUT to normal ACK NAK operation POR STLEP1OUT 0 Chip Reset STLEP1OUT 0 Bus Reset STLEP1OUT 0 Pwr Down Re...

Page 66: ...L handshake for an IN request directed to endpoint 2 Clear The CPU clears this bit to return EP2 IN to normal ACK NAK operation POR STLEP2IN 0 Chip Reset STLEP2IN 0 Bus Reset STLEP2IN 0 Pwr Down Read...

Page 67: ...an IN request directed to endpoint 3 Clear The CPU clears this bit when it receives a Clear_Feature Halt request directed to EP3 IN POR STLEP3IN 0 Chip Reset STLEP3IN 0 Bus Reset STLEP3IN 0 Pwr Down R...

Page 68: ...ves POR STLSTAT 0 Chip Reset STLSTAT 0 Bus Reset STLSTAT 0 Pwr Down Read only Programming Notes Endpoint 0 has three stall bits to account for the status stage and the optional IN and OUT data stages...

Page 69: ...he SIE clears this bit to disable the SUDAV Interrupt Request POR SUDAVIE 0 Chip Reset SUDAVIE 0 Bus Reset SUDAVIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable bits are...

Page 70: ...tion of the eight setup data bytes in a CONTROL transfer Clear The CPU clears this bit by writing a 1 to it POR SUDAVIRQ 0 Chip Reset SUDAVIRQ 0 Bus Reset SUDAVIRQ 0 Pwr Down Read only Programming Not...

Page 71: ...est page 66 Read The CPU does eight reads to this register to retrieve the eight SETUP bytes POR SUDFIFO 0 Chip Reset SUDFIFO 0 Bus Reset SUDFIFO 0 Pwr Down No read or write Programming Notes The MAX3...

Page 72: ...clears this bit to disable the SUSPEND Interrupt Request POR SUSPIE 0 Chip Reset SUSPIE 0 Bus Reset SUSPIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable bits are cleared...

Page 73: ...3 milliseconds of no bus traffic Clear The CPU clears this bit by writing a 1 to it POR SUSPIRQ 0 Chip Reset SUSPIRQ 0 Bus Reset SUSPIRQ 0 Pwr Down Read only Programming Notes The CPU responds to thi...

Page 74: ...e 68 Clear The CPU clears this bit to enable the URESDN IRQ POR URESDNIE 0 Chip Reset URESDNIE 0 Bus Reset No change Pwr Down Read only Programming Notes This is one of two bits that are not cleared d...

Page 75: ...terrupt Request Location USBIRQ 7 Set The SIE sets this bit when it has detected the end of a USB bus reset Clear The CPU clears this bit by writing a 1 to it POR URESDNIRQ 0 Chip Reset URESDNIRQ 0 Bu...

Page 76: ...Clear The CPU clears this bit to disable the USB Reset Interrupt Request POR URESIE 0 Chip Reset URESIE 0 Bus Reset No change Pwr Down Read only Programming Notes This is one of two bits that are not...

Page 77: ...st Location USBIRQ 3 Set The SIE sets this bit when it detects a USB bus reset at least 2 5 usec of the SE0 bus state Clear The CPU clears this bit by writing a 1 to it POR URESIRQ 0 Chip Reset URESIR...

Page 78: ...U clears this bit to disable the VBUS Interrupt Request POR VBUSIE 0 Chip Reset VBUSIE 0 Bus Reset VBUSIE 0 Pwr Down Read only Programming Notes Because most of the Interrupt Enable bits are cleared d...

Page 79: ...0 1 transition Clear The CPU clears this bit by writing a 1 to it POR VBUSIRQ 0 Chip Reset VBUSIRQ 0 Bus Reset VBUSIRQ 0 Pwr Down Read only Programming Notes This IRQ bit provides an easy way for a se...

Page 80: ...ly to occur in a self powered device which has its own power supply and does not directly power the pullup resistor from the VBUS pin Only when the host activates the downstream port by turning on VBU...

Page 81: ...OUTFIFO 14 EP2DISAB 15 EP2INAK 16 EP2INBC 17 EP2INFIFO 18 EP3DISAB 19 EP3INAK 20 EP3INBC 21 EP3INFIFO 22 FDUPSPI 23 FNADDR 26 GPIN0 27 GPIN1 28 GPIN2 29 GPIN3 30 GPOUT0 31 GPOUT1 32 GPOUT2 33 GPOUT3 3...

Page 82: ...RQ 53 POSINT 54 PWRDOWN 55 RWUDNIE 56 RWUDNIRQ 57 SIGRWU 58 STLEP0IN 59 STLEP0OUT 60 STLEP1OUT 61 STLEP2IN 62 STLEP3IN 63 STLSTAT 64 SUDAVIE 65 SUDAVIRQ 66 SUDFIFO 67 SUSPIE 68 SUSPIRQ 69 URESDNIE 70...

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