OUT1DAVIRQ
Meaning:
Endpoint 1 OUT Data Available Interrupt Request.
Location:
EPIRQ.2
Set:
The
SIE
sets this bit when it has successfully received (and ACK’d) an OUT
data packet to EP1-OUT.
Clear:
The CPU clears this bit by writing a 1 to it. This also arms the endpoint for
another transfer.
POR:
OUT1DAVIRQ=0
Chip Reset:
OUT1DAVIRQ=0
Bus Reset:
OUT1DAVIRQ=0
Pwr Down:
Read-only
Programming Notes:
EP1OUT is a double-buffered endpoint, meaning that there are two FIFOS and byte count
registers. Double buffering allows USB data simultaneously to move into one FIFO while the
CPU reads data from the other. This improves bandwidth performance in many systems.
The OUT1DAVIRQ flag logic makes the double buffering invisible to the programmer. For
example, assume that both buffers are available and therefore OUT1DAVIRQ=0. When an OUT
packet arrives, OUT1DAVIRQ makes a 0-1 transition to indicate availability of the first packet.
For a single-buffered endpoint, if another OUT packet arrived over EP1-OUT before the CPU
had time to drain the FIFO, the SIE would respond with a NAK handshake to indicate that the
endpoint was not available to accept data.
However with the double buffered endpoint, the second OUT packet is accepted and ACK’d
because the second buffer is available for data. If a third OUT packet arrives before either FIFO
is drained, the SIE NAKS the transfer to indicate that both FIFOS are full. When the CPU
finishes reading the first FIFO and clears the OUT1DAVIRQ bit (by writing one to it), it
immediately makes another 0-1 transition to indicate data is available in the second FIFO.
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