POSINT
Meaning:
The
INT output pin (if set for edge output) is positive-edge active. This bit takes
effect only if INTLEVEL=0 (page 45).
Location:
PINCTL.2
Set:
The CPU sets this bit to cause the INT pin to make a 0-1 transition whenever an
interrupt requires service.
Clear:
The CPU clears this bit to cause the INT pin to make a 1-0 transition whenever an
interrupt requires service.
POR:
POSINT=0
Chip Reset:
No change
Bus Reset:
No change
Pwr Down:
Read-write
Programming Notes:
Clear first IRQ,
second IRQ
still active
INTLEVEL=1
POSINT=X
First IRQ
Active
Second IRQ
Active
Clear last
pending IRQ
Single
IRQ
Clear
IRQ
(1)
(2)
(1) Width determined by clearing the IRQ. (2) Fixed at ~20 usec.
INTLEVEL=0
POSINT=X
INTLEVEL=0
POSINT=X
Figure 9. INT pin behavior depending on INTLEVEL and POSINT bits.
The setting of this bit has no effect if INTLEVEL=1 (page 45).
The edge sensitive mode supply an edge every time a new interrupt becomes active, or whenever
the SPI master clears an IRQ while others are pending. As Figure 9 shows, the width of the edge-
active pulse can vary. If only one IRQ is active, as shown by the first pulse, the width depends on
how long the SPI master takes to clear the IRQ bit. If others are pending when a new IRQ asserts
or when the SPI master clears an IRQ, the pulse width is fixed at about 20 microseconds.
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